1. An automated computer implemented method for dynamically adjusting discount rates for a card transaction, wherein the method is executed by a programmed computer processor, the computer implemented method comprising the steps of:
identifying credit worthiness of at least one consumer, at an issuing module using the programmed computer processor;
assigning a first credit level to a line of credit associated with a credit product for the at least one consumer, at the issuing module using the programmed computer processor, wherein the credit product is accepted at an identified one or more merchants, wherein at least one of the identified one or more merchants is within a closed loop network;
assigning a second credit level to a second line of credit associated with the credit product, at the issuing module using the programmed computer processor, wherein the second line of credit is for general use within a card association network;
assigning a first financing charge to the first line of credit;
assigning a second financing charge to the second line of credit, at the issuing module using the programmed computer processor, wherein the first financing charge is different from the second financing charge;
determining a discount rate for at least one transaction based at least in part on the credit worthiness of the at least one consumer and based at least in part on merchant-related data, using the programmed computer processor; and
applying the discount rate when at least one transaction is made with the credit product at the identified one or more merchants within the closed loop network, at the rate determining module using the programmed computer processor wherein the discount rate is paid by the identified one or more merchants;
wherein the discount rate is dynamically adjusted as the credit worthiness of the at least one consumer changes.
2. The method of claim 1, wherein the credit worthiness is determined by a FICO risk score.
3. The method of claim 1, wherein the second line of credit is dynamically adjusted.
4. The method of claim 1, wherein the step of determining the discount rate is based at least in part on the credit worthiness of the at least one consumer further comprises the step of:
determining the discount rate based at least in part on merchant-related data comprising at least one of sales data, inventory data, economy data, type of channel and type of merchandise.
5. The method of claim 4, further comprising the step of:
dynamically adjusting the discount rate as the merchant-related data is adjusted.
6. The method of claim 1, wherein a transaction type is identified at a point of sale for routing the transaction to an appropriate network.
7. The method of claim 1, wherein an interchange fee associated with the general purpose line is based at least in part on the credit worthiness of the at least one consumer.
8. The method of claim 7, wherein the interchange fee is dynamically adjusted as the credit worthiness of the at least one consumer fluctuates.
9. The method of claim 1, wherein the step of determining a discount rate involves assigning a table of discount rates and selecting the appropriate discount rate for each transaction.
10. The method of claim 1, wherein the at least one consumer represents a class of consumers.
11. The method of claim 1, wherein the identified one or more merchants are within a closed loop network.
12. A computer implemented system for dynamically adjusting discount rates for a card transaction, the computer implemented system comprising: a processor;
an issuing module for identifying credit worthiness of at least one consumer; assigning a first credit level to a line of credit associated with a credit product for the at least one consumer wherein the credit product is accepted at an identified one or more merchants within a closed loop network; assigning a second credit level to a second line of credit associated with the credit product wherein the second line of credit is for general use within a card association network; and assigning a first financing charge to the line of credit; and assigning a second financing charge to the second line of credit, wherein the first financing charge is different from the second financing charge;
a rate determining module for determining a discount rate for at least one transaction based at least in part on the credit worthiness of the at least one consumer and based at least in part on merchant-related data; and
applying the discount rate when the at least one transaction is made with the credit product at the identified one or more merchants within the closed loop network, wherein the discount rate is paid by the identified one or more merchants;
wherein the discount rate is dynamically adjusted as the credit worthiness of the at least one consumer; and
wherein the processor, the issuing module, the rate determining module are interoperatively connected.
13. The system of claim 12, wherein the credit worthiness is determined by a FICO risk score.
14. The system of claim 12, wherein the second line of credit is dynamically adjusted.
15. The system of claim 12, wherein the discount rate is further based at least in part on merchant-related data comprising at least one of sales data, inventory data, economy data, type of channel and type of merchandise.
16. The system of claim 15, wherein the discount rate is dynamically adjusted as the merchant-related data is adjusted.
17. The system of claim 12, wherein a transaction type is identified at a point of sale for routing the transaction to an appropriate network.
18. The system of claim 12, wherein an interchange fee associated with the general purpose line is based at least in part on the credit worthiness of the at least one consumer.
19. The system of claim 18, wherein the interchange fee is dynamically adjusted as the credit worthiness of the at least one consumer fluctuates.
20. The system of claim 12, wherein the rate determining module assigns a table of discount rates and identifies the appropriate discount rate for each transaction.
21. The system of claim 12, wherein the at least one consumer represents a class of consumers.
22. The system of claim 12, wherein the identified one or more merchants are within a closed loop network.
23. A computer program of instructions configured to be readable by at least one programmed computer processor to execute a computer process for performing the method as recited in claim 1.
24. An automated method for implementing a credit card product with multiple lines of credit, wherein the method is executed by a programmed computer processor, the method comprising the steps of:
implementing a general purpose line with a first credit level, at the issuing module using the programmed computer processor; and
implementing a private label line with a second credit level different from the first credit level, at the issuing module using the programmed computer processor;
wherein a first discount rate is applied to the general purpose line and a second discount rate based at least in part on the credit worthiness of the at least one consumer and based at least in part on merchant-related data is applied the private label line and wherein the first discount rate is different from the second discount rate; and
wherein the second discount rate is paid by one or more merchants associated with the private label line.
25. The method of claim 24, wherein the private label line has an adjustable discount rate.
26. A credit card product with multiple lines of credit, the credit card product comprising:
a general purpose line with a first credit level; and a private label line with a second credit level different from the first credit level;
wherein a first discount rate is applied to the general purpose line and a second discount rate based at least in part on the credit worthiness of the at least one consumer and based at least in part on merchant-related data is applied the private label line and wherein the first discount rate is different from the second discount rate; and
wherein the second discount rate is paid by one or more merchants associated with the private label line.
27. The product of claim 26, wherein the private label line has an adjustable discount rate.
28. A computer program of instructions configured to be readable by at least one processor for dynamically adjusting discount rates for a card transaction, the computer program comprising:
identifying means for identifying credit worthiness of at least one consumer;
assigning means for assigning a credit level to a line of credit associated with a credit product for the at least one consumer wherein the credit product is accepted at an identified one or more merchants;
assigning means for assigning a financing charge to the line of credit;
determining means for determining a discount rate for at least one transaction based at least in part on the credit worthiness of the at least one consumer and based at least in part on merchant-related data; and
applying means for applying the discount rate when at least one transaction is made with the credit product wherein the discount rate is paid by the identified one or more merchants;
wherein the applied discount rate is adjusted based on the credit worthiness of the at least one consumer;
wherein at least one of the identified one or more merchants is within a closed loop network.
29. An automated computer implemented method for dynamically adjusting discount rates for a card transaction, wherein the method is executed by a programmed computer processor, the computer implemented method comprising the steps of:
identifying credit worthiness of at least one consumer, using the programmed computer processor;
assigning a credit level to a line of credit associated with a credit product for the at least one consumer, using the programmed computer processor, wherein the credit product is accepted at an identified one or more merchants within a closed loop network;
assigning a financing charge to the line of credit, using the programmed computer processor;
determining a discount rate for at least one transaction based at least in part on the credit worthiness of the at least one consumer and merchant-related data comprising at least one of sales data, inventory data, and economy data, wherein the credit worthiness is determined by a FICO risk score, using the programmed computer processor;
assigning a second credit level to a second line of credit associated with the credit product, using the programmed computer processor, wherein the second line of credit is for general use within a card association network;
applying the discount rate when the at least one transaction is made with the credit product, using the programmed computer processor; wherein a transaction type is identified at a point of sale for routing the transaction to an appropriate network; wherein the discount rate is paid by the identified one or more merchants; and
dynamically adjusting the discount rate as the credit worthiness of the at least one consumer fluctuates and dynamically adjusting the discount rate as the merchant-related data is adjusted, using the programmed computer processor;
wherein the applied discount rate is adjusted based on the credit worthiness of the at least one consumer; wherein an interchange fee associated with the general purpose line is based at least in part on the credit worthiness of the at least one consumer; and the interchange fee is dynamically adjusted as the credit worthiness of the at least one consumer fluctuates.
30. An automated computer implemented method for dynamically adjusting discount rates for a card transaction, wherein the method is executed by a programmed computer processor, the computer implemented method comprising the steps of:
identifying credit worthiness of at least one consumer, using the programmed computer processor;
assigning a credit level to a line of credit associated with a credit product for the at least one consumer, using the programmed computer processor;
assigning a financing charge to the line of credit, using the programmed computer processor;
determining a discount rate for at least one transaction based at least in part on the credit worthiness of the at least one consumer and merchant-related data comprising at least one of sales data, inventory data, and economy data, wherein the credit worthiness is determined by a risk score, using the programmed computer processor;
assigning a second credit level to a second line of credit associated with the credit product, using the programmed computer processor, wherein the second line of credit is for general use within a card association network;
applying the discount rate when at least one transaction is made with the credit product, using the programmed computer processor; wherein a transaction type is identified at a point of sale for routing the transaction to an appropriate network; wherein the discount rate is paid by the identified one or more merchants; and
dynamically adjusting the discount rate as the credit worthiness of the at least one consumer fluctuates and as the merchant-related data is adjusted, using the programmed computer processor;
wherein the applied discount rate is adjusted based on the credit worthiness of the at least one consumer; wherein an interchange fee associated with the general purpose line is based at least in part on the credit worthiness of the at least one consumer; and the interchange fee is dynamically adjusted as the credit worthiness of the at least one consumer fluctuates.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory device, comprising:
a plurality of bit lines formed on a substrate and arranged substantially in a first plane and extending substantially in a first direction;
a plurality of layers, each layer having an array of memory cells;
a plurality of tree structures, at least one tree structure corresponding to each bit line, each tree structure having a trunk portion and at least one branch portion, each branch portion of a tree structure corresponding to at least one layer, the trunk portion of each tree structure extending from the substrate, each branch portion of a tree structure extending from the trunk portion of the tree structure, and each tree structure corresponding to a plurality of layers; and
a plurality of plate line groups, each plate line group including a plurality of plate lines and corresponding to at least one layer, each respective plate line group overlapping branch portions of each tree structure in at least one row of tree structures at a plurality of intersection regions, a memory cell being located at each intersection region in a layer.
2. The memory device according to claim 1, wherein at least one memory cell is a ferroelectric-capacitor memory cell.
3. The memory device according to claim 1, wherein at least one memory cell is a hysteretic-resistor memory cell.
4. The memory device according to claim 1, wherein the trunk portion of at least one tree structure includes a plurality of vias, and at least one via is offset from at least one other via.
5. The memory device according to claim 1, wherein the trunk portion of at least one tree structure includes a plurality of vias that are in line with each other.
6. The memory device according to claim 1, wherein each respective plate line group is arranged in a direction that is substantially perpendicular to a direction the branch portion of each tree structure extends.
7. The memory device according to claim 1, wherein the branch portions of each tree structure extend substantially in a direction that is parallel to the first direction.
8. The memory device according to claim 1, wherein the plurality of tree structures is arranged in a plurality of rows of tree structures.
9. The memory device according to claim 1, further comprising:
a plurality of cell layer lines extending substantially in the first direction;
a plurality of cell column lines extending in a direction that is substantial perpendicular to the first direction and overlapping the plurality of cell layer lines at a plurality of second intersection regions; and
a plurality of plate-line driver transistors arranged in a two-dimensional array, each respective plate-line driver transistor corresponding to and being located at a respective second intersection region, and a connection being formed between each plate line and the plate-line driver corresponding to the plate line.
10. The memory device according to claim 9, wherein each plate-line driver transistor has a control terminal, and
wherein a cell column line corresponding to each plate-line driver transistor is coupled to the control terminal of the plate-line driver transistor.
11. The memory device according to claim 9, wherein each plate-line driver transistor has a control terminal, and
wherein a cell layer line corresponding to each plate-line driver transistor is coupled to the control terminal of the plate-line driver transistor.
12. The memory device according to claim 1, further comprising:
a plurality of access lines formed on the substrate, extending in a direction that is substantially perpendicular to the first direction and overlapping the bit lines at a plurality of second intersection regions, each second intersection region corresponding to a tree structure, each access line further corresponding to a tree structure row; and
a plurality of access transistors, each respective access transistor corresponding to and being located at a respective second intersection region, each respective access transistor further being electrically disposed between the tree structure and the bit line corresponding to the second intersection region, each respective access transistor having a control terminal and further being coupled to the access line corresponding to the second intersection region.
13. The memory device according to claim 12, wherein each access line is a write line and each access transistor is a write transistor,
the memory device further comprising:
a plurality of read transistors that are each electrically disposed between a tree structure and the bit line corresponding to the tree structure;
a plurality of read lines formed on the substrate, extending in a direction that is substantially perpendicular to the first direction and overlapping the bit lines at a plurality of third intersection regions, each third intersection region corresponding to a tree structure, each read line further corresponding to a tree structure row; and
a plurality of read transistors, each respective read transistor corresponding to and being located at a respective third intersection region, each respective read transistor further being electrically disposed between the tree structure and the bit line corresponding to the third intersection region, each respective read transistor having a control terminal and further being coupled to the read line corresponding to the third intersection region.
14. The memory device according to claim 13, further comprising a plurality of gain transistors, each gain transistor corresponding to a read transistor and being disposed between the read transistor and the tree structure corresponding to the read transistor, each gain transistor including a control terminal that is coupled to the corresponding tree structure.
15. The memory device according to claim 1, further comprising:
a plurality of read lines formed on the substrate, extending in a direction that is substantially perpendicular to the first direction and overlapping the bit lines at a plurality of second intersection regions, each second intersection region corresponding to a tree structure, each read line further corresponding to a tree structure row and being electrically coupled to the read transistor that is electrically disposed between each corresponding tree structure and the bit line corresponding to the tree structure; and
a plurality of read transistors, each respective read transistor corresponding to and being located at a respective second intersection region, each respective read transistor further being electrically disposed between the tree structure and the bit line corresponding to the second intersection region, each respective read transistor having a control terminal and further being coupled to the read line corresponding to the second intersection region.
16. The memory device according to claim 15, further comprising a plurality of gain transistors, each gain transistor corresponding to a read transistor and being disposed between the read transistor and the tree structure corresponding to the read transistor, each gain transistor including a control terminal that is coupled to the corresponding tree structure.
17. The memory device according to claim 1, wherein at least one memory cell has ferroelectric material with a pillar-like structure.
18. The memory device according to claim 1, wherein a plurality of memory cells are connected by a ferroelectric wire.
19. The memory device according to claim 1, wherein a plurality of memory cells are connected by a ferroelectric film.
20. The memory device according to claim 1, further comprising:
at least one tree having a plurality of associated memory cells containing a first value;
at least one tree having a plurality of associated memory cells containing a second value that is different from the first value;
an averaging circuit outputting an average of an output of each tree having a plurality of associated memory cells containing the first value with an output of each tree having a plurality of associated memory cells containing the second value; and
a comparator circuit determining an output value of a selected memory cell of the memory device based on the output of the averaging circuit.
21. A memory device, comprising:
a plurality of bit lines formed on a substrate, arranged substantially in a first plane and extending substantially in a first direction;
a three-dimensional memory having a plurality of layers;
a plurality of plate lines arranged in each layer of the three-dimensional memory; and
a plurality of plate-line driver transistors formed on the substrate and arranged in a two-dimensional array, each plate-line driver transistor corresponding to a plate line.
22. The memory device according to claim 21, further comprising:
a plurality of cell layer lines extending substantially in the first direction;
a plurality of cell column lines extending in a direction that is substantial perpendicular to the first direction and overlapping the plurality of cell layer lines at a plurality of second intersection regions; and
wherein each respective plate-line driver transistor corresponding to and being located at a respective second intersection region, and a connection being formed between each plate line and the plate-line driver corresponding to the plate line.
23. The memory device according to claim 21, wherein each layer of the three-dimensional memory includes an array of memory cells.
24. The memory device according to claim 23, wherein at least one memory cell has ferroelectric material with a pillar-like structure.
25. The memory device according to claim 23, wherein a plurality of memory cells are connected by a ferroelectric wire.
26. The memory device according to claim 23, wherein a plurality of memory cells are connected by a ferroelectric film.
27. The memory device according to claim 23, wherein at least one memory cell is a ferroelectric-capacitor memory cell.
28. The memory device according to claim 23, wherein at least one memory cell is a hysteretic-resistor memory cell.
29. The memory device according to claim 21, further comprising:
at least one tree having a plurality of associated memory cells containing a first value;
at least one tree having a plurality of associated memory cells containing a second value that is different from the first value;
an averaging circuit outputting an average of an output of each tree having a plurality of associated memory cells containing the first value with an output of each tree having a plurality of associated memory cells containing the second value; and
a comparator circuit determining an output value of a selected memory cell of the memory device based on the output of the averaging circuit.