1. A computer system, comprising:
a computer chassis housing a processor and having an airflow pathway through the computer chassis;
a dust filter disposed in the airflow pathway;
a plurality of electrodes disposed across an area of the dust filter;
a voltage source having a negative terminal and a positive terminal; and
a controller for selectively coupling a first subset of the plurality of electrodes to the negative terminal and selectively coupling a second subset of the plurality of electrodes to the positive terminal, wherein a voltage differential between the first subset of electrodes and the second subset of electrodes is sufficient to cause electrostatic movement of dust from an area of the dust filter near the first subset of electrodes to an area of the dust filter near the second subset of electrodes.
2. The computer system of claim 1, wherein the first subset of electrodes is disposed above the second subset of electrodes to move the dust in a generally downward direction.
3. The computer system of claim 2, further comprising:
a damper disposed below the dust filter, wherein the damper opens into communication with a duct through the computer chassis to the rear of the computer chassis.
4. The computer system of claim 3, wherein the duct does not contain heat-generating components.
5. The computer system of claim 4, further comprising:
a fan that draws air through the duct to the rear of the computer chassis when the damper is open.
6. The computer system of claim 3, further comprising:
a fan that draws air through the airflow pathway.
7. The computer system of claim 6, wherein the fan draws air through the duct wherein the damper is open.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor over a substrate, the oxide semiconductor including a bottom surface, a top surface and side surfaces, the side surfaces extending in a channel length direction of the transistor, wherein a height of the oxide semiconductor is greater than a length of the oxide semiconductor at the bottom surface along a direction perpendicular to the channel length direction; and
a gate electrode along the top surface and the side surfaces with a gate insulating film between the gate electrode and the oxide semiconductor,
wherein the oxide semiconductor comprises a first region including crystals, and
wherein c-axes of the crystals in the first region are substantially perpendicular to a surface of the oxide semiconductor.
2. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In\u2014Zn-based oxide, a Sn\u2014Zn-based oxide, an Al\u2014Zn-based oxide, a Zn\u2014Mg-based oxide, a Sn\u2014Mg-based oxide, an In\u2014Mg-based oxide, an In\u2014Sn-based oxide, an In\u2014Ga-based oxide, an In\u2014Ga\u2014Zn-based oxide, an In\u2014Sn\u2014Zn-based oxide, an In\u2014Al\u2014Zn-based oxide, a Sn\u2014Ga\u2014Zn-based oxide, an Al\u2014Ga\u2014Zn-based oxide, a Sn\u2014Al\u2014Zn-based oxide, and an In\u2014Sn\u2014Ga\u2014Zn-based oxide.
3. A random access memory comprising the transistor according to claim 1 as a cell transistor.
4. A memory comprising the transistor according to claim 1 as a writing transistor.
5. The semiconductor device according to claim 1, wherein a corner portion of the oxide semiconductor has a curved shape.
6. The semiconductor device according to claim 1, wherein part of the oxide semiconductor comprises an N-type region comprising nitrogen, boron, or phosphorus.
7. A semiconductor device comprising a transistor, the transistor comprising:
an oxide semiconductor over a substrate, the oxide semiconductor including a bottom surface, a top surface and side surfaces, the side surfaces extending in a channel length direction of the transistor, wherein a height of the oxide semiconductor is greater than a length of the oxide semiconductor at the bottom surface along a direction perpendicular to the channel length direction; and
a gate electrode along the top surface and the side surfaces with a gate insulating film between the gate electrode and the oxide semiconductor,
wherein the oxide semiconductor comprises a first region including crystals,
wherein c-axes of the crystals in the first region are substantially perpendicular to a surface of the oxide semiconductor,
wherein the first region is in contact with the top surface of the oxide semiconductor,
wherein the oxide semiconductor comprises a second region being in contact with one of the side surfaces of the oxide semiconductor,
wherein the second region includes crystals, and
wherein c-axes of the crystals in the second region are substantially perpendicular to the one of the side surfaces of the oxide semiconductor.
8. The semiconductor device according to claim 7, wherein the oxide semiconductor comprises any one of indium oxide, zinc oxide, tin oxide, an In\u2014Zn-based oxide, a Sn\u2014Zn-based oxide, an Al\u2014Zn-based oxide, a Zn\u2014Mg-based oxide, a Sn\u2014Mg-based oxide, an In\u2014Mg-based oxide, an In\u2014Sn-based oxide, an In\u2014Ga-based oxide, an In\u2014Ga\u2014Zn-based oxide, an In\u2014Sn\u2014Zn-based oxide, an In\u2014Al\u2014Zn-based oxide, a Sn\u2014Ga\u2014Zn-based oxide, an Al\u2014Ga\u2014Zn-based oxide, a Sn\u2014Al\u2014Zn-based oxide, and an In\u2014Sn\u2014Ga\u2014Zn-based oxide.
9. A random access memory comprising the transistor according to claim 7 as a cell transistor.
10. A memory comprising the transistor according to claim 7 as a writing transistor.
11. The semiconductor device according to claim 7, wherein a corner portion of the oxide semiconductor has a curved shape.
12. The semiconductor device according to claim 7, wherein part of the oxide semiconductor comprises an N\u2014type region comprising nitrogen, boron, or phosphorus.