1. A method for manufacturing a thin-film photovoltaic cell, the method comprising:
providing a substrate;
forming a imprinted surface on the substrate; and
depositing one or more thin-film photovoltaic layers on the imprinted surface.
2. The method of claim 1, wherein the substrate includes polyimide.
3. The method of claim 1, wherein the substrate includes a non-imprintable portion and an imprintable portion.
4. The method of claim 3, wherein the non-imprintable portion includes glass.
5. The method of claim 3, wherein the imprintable portion includes polyimide.
6. The method of claim 1, wherein forming an imprinted surface on the substrate includes hot embossing.
7. The method of claim 1, wherein forming an imprinted surface on the substrate includes soft lithography.
8. The method of claim 1, wherein forming an imprinted surface on the substrate includes micro-contact imprinting.
9. The method of claim 1, wherein forming an imprinted surface on the substrate includes ultraviolet lithographical imprinting.
10. The method of claim 1, further comprising disposing a filler layer on the one or more thin-film photovoltaic layers.
11. The method of claim 10, wherein the filler layer is substantially transparent to a wavelength of interest.
12. The method of claim 1, wherein the one or more thin-film photovoltaic layers include a hole conductor layer, an active layer and an electron conductor layer.
13. A method for manufacturing a thin-film photovoltaic cell, the method comprising:
providing an imprintable substrate;
imprinting the substrate to define a rough surface on the substrate;
providing one or more thin-film photovoltaic layer on the rough surface; and
providing a filler layer on the one or more thin-film photovoltaic layers to form a substantially planar top surface.
14. The method of claim 13, wherein the imprintable substrate includes polyimide.
15. The method of claim 13, wherein the imprintable substrate includes a glass layer with an imprintable polyimide layer disposed on the glass layer.
16. The method of claim 13, wherein imprinting the substrate includes hot embossing, soft lithography, micro-contact imprinting, or ultraviolet lithographical imprinting.
17. The method of claim 13, wherein the filler layer is substantially transparent to a wavelength of interest.
18. The method of claim 13, wherein the one or more thin-film photovoltaic layers include a hole conductor layer, an active layer and an electron conductor layer.
19. A thin-film photovoltaic cell, comprising:
a substrate layer having an imprinted surface;
one or more thin-film photovoltaic layers disposed above the imprinted surface; and
a filler layer disposed above the one or more thin-film photovoltaic layers, wherein the filler layer has a substantially planar top surface.
20. The thin-film photovoltaic cell of claim 19, wherein the substrate includes a glass layer with an imprintable polyimide layer disposed on the glass layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for providing a charge device model (CDM) damage protection for a semiconductor circuit, the method comprising:
coupling a CDM immunity module to a substrate of at least one device to be protected from the CDM damage; and
coupling the CDM immunity module to a ground pad,
wherein the CDM immunity module and the ground pad dissipate CDM charges to avoid damage to an oxide layer of the device.
2. The method of claim 1 wherein the CDM immunity module is a diode.
3. The method of claim 2 wherein the device is a NMOS transistor and its substrate is connected to the diode’s anode.
4. The method of claim 2 wherein the device is a PMOS transistor and its substrate is connected to the diode’s cathode.
5. The method of claim 1 wherein the CDM immunity module is a diode coupled parallel with at least one capacitor.
6. The method of claim 1 wherein the ground pad is connected to at least one metalization layer of the device.
7. The method of claim 1 wherein the ground pad is connected to one or more metalization layers of the device as they are processed sequentially for forming the device.
8. The method of claim 1 wherein the CDM immunity module is placed in one or more corner regions of the semiconductor circuit.
9. The method of claim 1 wherein the semiconductor circuit further comprises at least one electrostatic discharge (ESD) protection module in conjunction with the CDM immunity module.
10. The method of claim 9 wherein the ESD protection module is coupled between the ground pad and a regular pad of the semiconductor circuit.
11. The method of claim 10 wherein the ESD protection module is a NMOS transistor with its gate and source connected to the ground pad, and its drain connected to the regular pad.
12. The method of claim 9 wherein the ESD protection module further comprises a diode connected between the gate and source thereof.
13. A semiconductor circuit with charge device model (CDM) damage protection, the circuit comprising:
a CDM immunity module coupled to a substrate of at least one device in a core circuit; and
a CDM ground pad coupled to the CDM immunity module,
wherein the CDM immunity module and the CDM ground pad dissipate CDM charges to avoid damage to an oxide layer of the device.
14. The circuit of claim 13 wherein the CDM immunity module is a diode.
15. The circuit of claim 14 wherein the device is a NMOS transistor and its substrate is connected to the diode’s anode.
16. The circuit of claim 14 wherein the device is a PMOS transistor and its substrate is connected to the diode’s cathode.
17. The circuit of claim 13 wherein the CDM immunity module is a diode coupled parallel with at least one capacitor.
18. The circuit of claim 13 wherein the CDM ground pad is connected to one or more metalization layers of the device as they are processed for forming the device.
19. The circuit of claim 13 wherein the CDM immunity module is placed in one or more corner regions of the semiconductor circuit.
20. The circuit of claim 13 further comprising at least one electrostatic discharge (ESD) protection module in conjunction with the CDM immunity module, wherein the ESD protection module is coupled between the CDM ground pad and a regular pad of the semiconductor circuit.
21. The circuit of claim 20 wherein the ESD protection module is a NMOS transistor with its gate and source connected to the CDM ground pad, and its drain connected to the regular pad.
22. A charge device model (CDM) immunity module used in a semiconductor circuit for CDM damage protection, the CDM immunity module comprising:
a CDM ground pad; and
a diode coupled between the CDM ground pad and a substrate of at least one device in a core circuit,
wherein the diode and the CDM ground pad dissipate CDM charges to avoid damage to an oxide layer of the device.
23. The module of claim 22 wherein the device is an NMOS transistor and its substrate is connected to the diode’s anode.
24. The module of claim 22 wherein the device is a PMOS transistor and its substrate is connected to the diode’s cathode.
25. The module of claim 22 further comprising at least one capacitor coupled parallel with the diode.
26. The module of claim 22 wherein the CDM ground pad is connected to one or more metalization layers of the device as they are processed for forming the device.
27. The module of claim 22 wherein the CDM ground pad is a regular ground pad of the semiconductor circuit.