1. A method of forming a semiconductor device, the method comprising:
siliciding a source region and a drain region of a first transistor formed on a substrate, the first transistor having a gate electrode with spacers formed alongside the gate electrode;
forming a dielectric layer over the gate electrode, the spacers, the source region and the drain region, the dielectric layer being different than the spacers and having a thickness less than the gate electrode;
removing the dielectric layer over the gate electrode; and
siliciding the gate electrode of the first transistor.
2. The method of claim 1 wherein the step of siliciding the source region and the drain region is performed during the same process steps.
3. The method of claim 1 wherein the step of siliciding the source region and the drain region includes partially siliciding the gate electrode.
4. The method of claim 1 wherein the step of siliciding the gate electrode is performed by substantially fully siliciding the gate electrode.
5. The method of claim 1 wherein the step of siliciding the gate electrode is performed by forming a first metal layer on the gate electrode and annealing.
6. The method of claim 5 wherein the first metal layer comprises a plurality of layers.
7. The method of claim 1 wherein the step of siliciding the drain and the source are performed by forming a first metal layer on the source and the drain and annealing, and the step of siliciding the gate electrode is performed by forming a second metal layer on the gate electrode and annealing.
8. The method of claim 7 wherein the first metal layer is a metal different from the second metal layer.
9. The method of claim 7 wherein the second metal layer is a plurality of layers.
10. The method of claim 7 wherein the step of siliciding the source and the drain includes partially siliciding the gate electrode.
11. The method of claim 1 wherein the dielectric layer comprises silicon nitride or silicon oxynitride.
12. The method of claim 1 further comprising the step of forming a silicon oxide layer over the dielectric layer.
13. A method of forming a semiconductor device, the method comprising:
siliciding a first sourcedrain region of a first transistor;
siliciding a second sourcedrain region of a second transistor;
forming a dielectric layer over the sourcedrain region and a first gate electrode of the first transistor and the sourcedrain region and a second gate electrode of the second transistor;
removing the dielectric layer over the first gate electrode and the second gate electrode;
siliciding the first gate electrode of the first transistor; and
siliciding the second gate electrode of the second transistor in a different process step as the step of siliciding the fist gate electrode.
14. The method of claim 13 wherein the step of siliciding the first sourcedrain region is performed by depositing a first metal layer and annealing.
15. The method of claim 14 wherein the first metal layer is a plurality of layers.
16. The method of claim 13 wherein the step of siliciding the first sourcedrain region and the step of siliciding the second sourcedrain region is performed with different metals.
17. The method of claim 13 wherein the step of siliciding the first gate electrode and the step of siliciding the second gate electrode is performed with different metals.
18. The method of claim 13 wherein the step of siliciding the first sourcedrain region includes partially siliciding the first gate electrode.
19. The method of claim 13 wherein the step of siliciding the second sourcedrain region includes partially siliciding the second gate electrode.
20. The method of claim 13 wherein the step of siliciding the first gate electrode is performed by substantially fully siliciding the first gate electrode.
21. The method of claim 13 wherein the step of siliciding the second gate electrode is performed by substantially fully siliciding the second gate electrode.
22. The method of claim 13 wherein the step of siliciding the first gate electrode is performed by forming a third metal layer on the first gate electrode and annealing.
23. The method of claim 13 wherein the step of siliciding the second gate electrode is performed by forming a fourth metal layer on the second gate electrode and annealing.
24. The method of claim 13 wherein the dielectric layer comprises silicon nitride or silicon oxynitride.
25. The method of claim 13 further comprising the step of forming a silicon oxide layer over the dielectric layer.
26. A semiconductor device comprising:
a first transistor; and
a second transistor,
wherein each of the first transistor and the second transistor includes a source, a drain, a gate electrode, and spacers formed alongside the gate electrode, the gate electrode of the first transistor and the gate electrode of the second transistor being silicided with different metals, and wherein a dielectric layer having a thickness less than a thickness of the gate electrode covers at least a portion of the source and the drain of the first and second transistors, the dielectric layer and the spacers being different layers.
27. The semiconductor device of claim 26 wherein the gate electrode of the first transistor is substantially fully silicided.
28. The semiconductor device of claim 26 wherein the gate electrode of the second transistor is substantially fully silicided.
29. The semiconductor device of claim 26 wherein the source and the drain of the first transistor is silicided with a first metal and the source and the drain of the second transistor are silicided with a second metal.
30. The semiconductor device of claim 26 wherein the source and the drain of the first transistor is silicided with a metal selected from the group comprising nickel, cobalt, copper, molybdenum, titanium, tantalum, tungsten, erbium, zirconium, platinum, and a combination thereof.
31. The semiconductor device of claim 26 wherein the gate electrode of the first transistor is silicided with a metal selected from the group comprising nickel, cobalt, copper, molybdenum, titanium, tantalum, tungsten, erbium, zirconium, platinum, and a combination thereof.
32. The semiconductor device of claim 26 wherein the source and the drain of the second transistor is silicided with a metal selected from the group comprising nickel, cobalt, copper, molybdenum, titanium, tantalum, tungsten, erbium, zirconium, platinum, and a combination thereof.
33. The semiconductor device of claim 26 wherein the gate electrode of the second transistor are silicided with a metal selected from the group comprising nickel, cobalt, copper, molybdenum, titanium, tantalum, tungsten, erbium, zirconium, platinum, and a combination thereof.
34. A method of forming a semiconductor device, the method comprising:
forming a nitrogen-containing dielectric layer over a gate electrode, a source region, and a drain region of a first transistor formed on a substrate;
removing the nitrogen-containing dielectric layer over the gate electrode;
forming a first metal layer over the gate electrode and the nitrogen-containing dielectric layer, the first metal layer having a non-planar surface; and
siliciding the gate electrode of the first transistor.
35. The method of claim 34 further comprising siliciding the source region and the drain region.
36. The method of claim 35 wherein the siliciding the source region and the drain region includes partially siliciding the gate electrode.
37. The method of claim 34 wherein the siliciding the gate electrode is performed by substantially fully siliciding the gate electrode.
38. The method of claim 34 wherein the siliciding the gate electrode is performed by annealing.
39. The method of claim 34 wherein the first metal layer comprises a plurality of layers.
40. The method of claim 34 wherein the nitrogen-containing dielectric layer comprises silicon nitride or silicon oxynitride.
41. The method of claim 34 further comprising the step of forming a silicon oxide layer over the nitrogen-containing dielectric layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An adaptor to link a standard jack and a standard plug, the adaptor comprising:
a jack adaptor with a principal axis for connecting a standard jack to a polarized and rugged jack interface, the jack adaptor comprising along the principal axis a standardized interface surface to interface with the standard jack, a first casing with a first end plate having a plurality of polarized rugged tabs along the principal axis for forming the polarized, rugged jack interface, and the polarized and rugged interface; and
a plug adaptor with a secondary axis for connecting a standard plug to a polarized, rugged plug interface, the plug adaptor comprising along the secondary axis a standardized interface to interface with a plug, and a second casing with a second end plate to interface with at least two polarized notches and the plug interface;
wherein when the plug interface is connected to the jack interface for connecting the standard jack to the standard plug, the first end plate is adjacent to the second end plate and the at least two polarized rugged tabs are mated without being bent to the polarized notches, and
wherein the first end plate has a surface perpendicular to the principal axis and the plurality of polarized rugged tabs extend from the surface in a direction parallel to the principal axis.
2. The adaptor of claim 1, wherein the second casing is a threaded portion on a body portion of the plug adaptor and a spanner nut.
3. The adaptor for a connector of claim 2, wherein the threaded portion includes a flat portion.
4. The adaptor of claim 1, wherein the polarized notches and the polarized rugged tabs are distributed around the periphery of the first end plate and the second end plate at regular intervals.
5. The adaptor of claim 4, wherein the regular interval is 180 degrees for a configuration with two polarized rugged tabs.
6. The adaptor of claim 4, wherein the regular interval is a configuration with three polarized rugged tabs, the regular interval being selected from a group consisting of a 100\xb0160\xb0100\xb0 configuration, a 110\xb0140\xb0110\xb0 configuration, a 120\xb0120\xb0120\xb0 configuration, a 130\xb0100\xb0130\xb0 configuration, and a 140\xb080\xb0140\xb0 configuration.
7. The adaptor of claim 1, wherein the jack is a quick-lock RC connector jack interface.
8. A method for keying one or more mating connector pairs, the connectors including a first connector along a principal axis comprising along the principal axis a first casing with a first end plate having a plurality of polarized rugged tabs, a first cable holder and a jack interface and second connector with a secondary axis comprising along the secondary axis a second casing, a second cable holder with a second end plate with at least two polarized notches and the plug interface, the method including the steps of:
placing the first connector on a first end of a cable to connect at the first cable holder;
placing the second connector on a second end of a cable to connect at the second cable holder; and
mating the rugged tabs on the first end plate to the notches of the second end plate to connect the first connector to the second connector so the first end of the cable is connected to the second end of the cable.
9. The method of claim 8, wherein the first connector includes a threaded portion and a spanner nut with the second end plate.