1. A friction brake assembly to act between a pair of relatively moveable components, comprising:
a braked member connected to one of said components,
a carrier connected to the other of said components;
a friction pad attached to said carrier for engagement with said brake member;
a first actuator operable upon said carrier to move said friction into engagement with said brake member;
a second actuator operable upon said carrier to move said friction pad away from said brake member; and
a control to operate selectively said first and second actuator.
2. A friction brake according to claim 1 wherein a resilient element is interposed between said first actuator and said carrier to maintain a bias against said brake member.
3. A friction brake according to claim 2 wherein said resilient element is a beam projection from said carrier.
4. A friction brake assembly according to any preceding claim wherein said first and said second actuators each comprise at least one shape memory alloy element.
5. A friction brake assembly according to claim 4 wherein said shape memory alloy element is a tensile element and said controller change the length of said element to actuate said brake.
6. A friction brake assembly according to claim 5 wherein said controller supplies an electrical current to respective ones of said elements to change the length thereof.
7. A friction brake assembly according to any preceding claim wherein said braked member is a drum rotatably mounted on said other member and said carrier is pivotally secured to said actuator for movement into or out of engagement with said drum.
8. A friction brake assembly according to claim 7 wherein said carrier includes a portion extending radially relative to said drum and said actuators and between spaced locations on said other member and said portion.
9. A friction brake assembly according to claim 8 wherein said portion is a flexible beam to couple resiliently said actuators to said carrier.
10. A friction brake assembly according to claim 8 or 9 wherein said actuators are tensile members formed from a shape memory alloy.
11. A friction brake assembly according to claim 10 wherein each of said actuators includes a plurality of tensile members arranged in parallel.
12. A friction brake assembly according to claim 11 wherein said members are electrically connected in series and a current passing through said tensile members effects foreshortening of said members.
13. A friction brake assembly according to any one of claims 7 to 12 wherein said carrier is pivotally mounted for movement about an axis parallel to but spaced from the axis of rotation of said drum.
14. A prosthesis having a pair of limbs pivotally connected on one another by a mechanical joint, an actuator connected between said limbs to effect relative rotation there between and a brake acting to inhibit such relative motion, said brake being operative upon said actuator to inhibit further movement in said joint.
15. A prosthesis according to claim 14 wherein said actuator includes a pair of relatively displaceable components to change the length of said actuator and said brake acts between said displaceable components.
16. A prosthesis according to claim 15 wherein said components are interconnected by a screw thread such that relative rotation there between causes a change in the length of said actuator and said brake acts to inhibit relative rotation.
17. A prosthesis according to claim 16 wherein said brake includes a rotatable drum and a carrier having a brake shoe engageable with said drum.
18. A prosthesis according to claim 17 wherein said shoe is engageable with said drum by foreshortening of a shape memory alloy tensile member.
19. A prosthesis according to claim 17 wherein said shoe is releasable from said drum by foreshortening of a shape memory alloy tensile member.
20. A prosthesis according to either claim 18 or 19 wherein said tensile member is connected to said shoe through a resilient connection.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit comprising:
an input to receive a first operand, the first operand including a first plurality of bits;
an input to receive a second operand, the second operand including a second plurality of bits;
a first circuit for providing a length indication; and
a logic circuit for providing an indication of a match between a logical sum of the first operand and the second operand with a set of bits of a third operand, wherein a length of the set of bits is determined by the length indication,
wherein the logic circuit generates the indication of the match by performing a plurality of bit logic operations, wherein each of the plurality of bit logic operations includes a logic operation on a bit of the first operand of a corresponding bit location, a bit of a second operand of the corresponding bit location, and a bit of the third operand of the corresponding bit location to generate a result and comparing the result with a carry indication generated from a logic operation on bits including bits of an immediately less significant bit location from the corresponding bit location, wherein each of the bit logic operations of the plurality of bit logic operations is performed for a different corresponding bit location of a plurality of bit locations.
2. The circuit of claim 1 further comprises:
a first carry determination circuit, the first carry determination circuit generating a first carry indication of at least one bit of carry bits of an add operation of the first operand and the second operand; and
a selection circuit;
wherein the selection circuit selects, based on the length indication, one of a group consisting of a bit of the first carry indication and a second carry indication generated from a logic operation on one bit of the first operand of a first bit location, one bit of the second operand of the first bit location, and one bit of the third operand of the first bit location, as the carry indication for the bit logic operation of an adjacent less significant bit location to the first bit location.
3. The circuit of claim 2 wherein:
for the bit location, a bit logic operation of the plurality of bit logic operations is for generating a result of a bit addition of a bit of the first operand, a bit of a second operand, and a bit of the third operand, and a comparison of the result with the one of the group.
4. The circuit of claim 2 wherein the bit logic operation for generating the result uses a first representation of a bit of the third operand, wherein the logic operation to generate the second carry indication uses a second representation of the bit of the third operation, wherein the second representation is complementary to the first representation.
5. The circuit of claim 1 wherein each of the plurality of bit logic operations performed by the logic circuit generates a bit result of a plurality of bit results, the logic circuit masks the plurality of bit results as per the length indication.
6. The circuit of claim 1 further comprising:
a first carry determination circuit, the first carry determination circuit generating a first carry indication of at least one bit of carry bits of an add operation of the first operand and the second operand;
wherein for each bit location of a first subset of the plurality of bit locations, the carry indication is selected, based on the length indication, from one of a group consisting of a bit of the first carry indication and a second carry indication generated from a logic operation on one bit of the first operand of an immediately less significant bit location to each bit location of the first subset, one bit of the second operand of the immediately less significant bit location to each bit location of the first subset, and one bit of the third operand of the immediately less significant bit location to each bit location of the first subset;
wherein for each bit of a second subset of the plurality of bit locations, the carry indication is generated from a logic operation on one bit of the first operand of an immediately less significant bit location to each bit location of the second subset, one bit of the second operand of the immediately less significant bit location to each bit location of the second subset, and one bit of the third operand of the immediately less significant bit location to each bit location of the second subset.
7. The circuit of claim 6 wherein a bit location of the first subset occurs at every fourth bit location of the plurality of bit locations wherein intervening three bit locations are bit locations of the second subset.
8. The circuit of claim 6 wherein the second subset has a greater number of bit locations of the plurality of bit locations than the first subset.
9. The circuit of claim 1 wherein the logic circuit is implemented in a content addressable memory, the third operand is stored in a storage location of a plurality of storage locations of the content addressable memory, the logic circuit generates a plurality of indications wherein each indication of the plurality is an indication of a match between a logical sum of the first operand and the second operand with a set of bits of a value from each storage location of the plurality of storage locations, wherein the length of the set of bits for each storage location is determined by the length indication.
10. The circuit of claim 9 wherein the length indication for a first storage location of the plurality of storage locations may indicate a different length than for a second storage location of the plurality of storage locations.
11. A method of comparing a logical sum of a first operand and second operand with a third operand, the method comprising:
receiving a first operand by logic circuitry;
receiving a second operand by the logic circuitry;
receiving a length indication by the logic circuitry; and
generating, by the logic circuitry, an indication of a match between a logical sum of the first operand and the second operand with a set of bits of a third operand, wherein the length of the set of bits is determined by the length indication;
wherein the generating includes:
performing a plurality of bit logic operations by the logic circuitry, wherein each bit logic operation on the plurality of bit logic operations corresponds to a bit position of a plurality of bit positions, wherein each of the plurality of bit logic operations includes performing a logic operation on a bit of the first operand of a corresponding bit location of the plurality of bit locations, a bit of a second operand of the corresponding bit location, and a bit of the third operand of the corresponding bit location to generate a result and comparing the result with a carry indication generated from a logic operation on bits including bits of an immediately less significant bit location from the corresponding bit location.
12. The method of claim 11 further comprising:
generating a first carry indication of at least one bit of a plurality of carry bits of an add operation of the first operand and the second operand;
selecting, based on the length indication, one of a group consisting of a bit of the first carry indication and a second carry indication generated from a logic operation on one bit of the first operand of a first bit location, one bit of the second operand of the first bit location, and one bit of the third operand of the first bit location;
wherein for a next significant bit location to the first bit location, the carry indication used for the bit logic operation of the plurality of logic operations as the selected one of the group.
13. The method of claim 12 wherein the logic operation for generating the second carry indication includes an addition operation of the one bit of the first operand of a first bit location, the one bit of the second operand of the first bit location, and the one bit of the third operand of the first bit location.
14. The method of claim 11 wherein:
the performing a plurality of bit logic operations generates a plurality of bit results; and
the generating an indication of a match includes masking the plurality of the bit results as per the length indication.
15. The method of claim 11 further comprising:
generating a first carry indication of at least one bit of a plurality of carry bits of an add operation of the first operand and the second operand;
wherein for each bit location of a first subset of the plurality of bit locations, the carry indication is selected, based on the length indication, from one of a group consisting of a bit of the first carry indication and a second carry indication generated from a logic operation on one bit of the first operand of an immediately less significant bit location to each bit location of the first subset, one bit of the second operand of the immediately less significant bit location to each bit location of the first subset, and one bit of the third operand of the immediately less significant bit location to each bit location of the first subset;
wherein for each bit of a second subset of the plurality of bit locations, the carry indication is a carry indication is generated from a logic operation on one bit of the first operand of an immediately less significant bit location to each bit location of the second subset, one bit of the second operand of the immediately less significant bit location to each bit location of the second subset, and one bit of the third operand of the immediately less significant bit location to each bit location of the second subset.
16. A content addressable memory, comprising:
an input to receive a first operand;
an input to receive a second operand;
a plurality of storage locations;
logic circuitry for providing a plurality of indications where each indication of the plurality of indications corresponds to a storage location of the plurality of storage locations, wherein each indication of the plurality of indications is an indication of a match between a logical sum of the first operand and the second operand with a set of bits of a value from a corresponding storage location of the plurality of storage locations;
wherein for each indication of the plurality of indications, the logic circuit generates the indication of the match by performing a plurality of bit logic operations, wherein each of the plurality of bit logic operations includes a logic operation on a bit of the first operand of a corresponding bit location, a bit of a second operand of the corresponding bit location, and a bit of the corresponding bit location of a value from the corresponding storage location to generate a result and comparing the result to a carry indication generated from a logic operation on bits including bits of an immediately less significant bit location from the corresponding bit location, wherein each of the bit operations of the plurality is performed for a different corresponding bit location of a plurality of bit locations.
17. The content addressable memory of claim 16 wherein for each indication of the plurality of indications, each of the plurality of bit logic operations includes a bit addition of the bit of the first operand of a corresponding bit location, the bit of a second operand of the corresponding bit location, and the bit of the corresponding bit location of the value from corresponding storage location.
18. The content addressable memory of claim 16 further comprising:
a first circuit for providing a length indication;
wherein for each indication of the plurality of indications, the bit length of the set of bits is determined by the length indication.
19. The content addressable memory of claim 16 further comprising:
a first carry determination circuit, the first carry determination circuit generating a first carry indication of at least one bit of carry bits of an add operation of the first operand and the second operand;
wherein for each indication of the plurality of indications:
for each bit location of at least some bit locations of the plurality of bit locations, the carry indication is selected, based on the length indication, from one of a group consisting of a bit of the first carry indication and a second carry indication generated from a logic operation on one bit of the first operand of an immediately less significant bit location to each bit location, one bit of the second operand of the immediately less significant bit location to each bit location, and one bit of a value from a corresponding storage location of the immediately less significant bit location to each bit location.
20. The content addressable memory of claim 16 further comprising:
a first carry determination circuit, the first carry determination circuit generating a first carry indication of at least one bit of carry bits of an add operation of the first operand and the second operand;
wherein for each indication of the plurality of indications:
for each bit location of a first subset of the plurality of bit locations, the carry indication is selected, based on the length indication, from one of a group consisting of a bit of the first carry indication and a second carry indication generated from a logic operation on one bit of the first operand of an immediately less significant bit location to each bit location of the first subset, one bit of the second operand of the immediately less significant bit location to each bit location of the first subset, and one bit of a value from a corresponding storage location of the immediately less significant bit location to each bit location of the first subset;
for each bit of a second subset of the plurality of bit locations, the carry indication is generated from a logic operation on one bit of the first operand of an immediately less significant bit location to each bit location of the second subset, one bit of the second operand of the immediately less significant bit location to each bit location of the second subset, and one bit of a value from a corresponding storage location of the immediately less significant bit location to each bit location of the second subset.