1. A semiconductor memory device, comprising:
a plurality of first pads;
a plurality of ports for performing a serial data communication with external devices through the first pads;
a plurality of banks for performing a parallel data communication with the plurality of ports;
a plurality of global data buses for supporting the parallel data communication between the plurality of ports and the plurality of banks; and
a test mode controller for performing a core test by converting the serial data communication into the parallel data communication during a selected core test mode,
wherein the test mode controller includes a mode setting unit for receiving a data transfer mode selection signal input through the global data buses and generating a mode setting signal in response to a mode register enable signal enabled during the core test mode.
2. The semiconductor memory device of claim 1, wherein the test mode controller further includes:
a clock generating unit for receiving an external clock signal and generating first and second internal clock signals in response to the mode setting signal; and
a test inputoutput (IO) control unit for bypassing a test signal input through the first pads in parallel to the global buses, and transferring an IO data signal between a plurality of second pads and the banks through the global data buses in response to the mode register enable signal in synchronization with the first and second internal clock signals.
3. The semiconductor memory device of claim 2, wherein the mode setting signal determines a data transfer mode of the IO data signal.
4. The semiconductor memory device of claim 3, wherein the first and second internal clock signals synchronize command signals, address signals, and the IO data signal to have a data transfer rate corresponding to the data transfer mode.
5. The semiconductor memory device of claim 2, wherein the first internal clock signal is used as a reference clock of the command signals and the address signals generated and used during the core test mode.
6. The semiconductor memory device of claim 2, wherein the second internal clock signal is used as a reference clock of the IO data signal input and output through the second pads during the core test mode.
7. The semiconductor memory device of claim 3, wherein the first internal clock signal has substantially the same waveform regardless of the data transfer mode.
8. The semiconductor memory device of claim 7, wherein the second internal clock signal has a different waveform according to the data transfer mode.
9. The semiconductor memory device of claim 8, wherein the second internal clock signal has a half period of the first internal clock signal.
10. The semiconductor memory device of claim 9, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising and falling edge of the second internal clock signal.
11. The semiconductor memory device of claim 8, wherein the second internal clock signal has substantially the same period as the first internal clock and a phase shifted by 90 degrees in comparison with the first internal clock signal.
12. The semiconductor memory device of claim 11, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising and falling edge of the first and second internal clock signals.
13. The semiconductor memory device of claim 8, wherein the second internal clock signal maintains one of a logic low level and a logic high level regardless of the first internal clock signal.
14. The semiconductor memory device of claim 13, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising and falling edge of the first internal clock signal.
15. The semiconductor memory device of claim 13, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising or falling edge of the first internal clock signal.
16. The semiconductor memory device of claim 7, wherein the second internal clock signal has substantially the same waveform as that of the first internal clock signal.
17. The semiconductor memory device of claim 16, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising and falling edge of the second internal clock signal.
18. The semiconductor memory device of claim 16, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising or falling edge of the second internal clock signal.
19. The semiconductor memory device of claim 2, wherein the global data buses include: a first bus for transferring the test signal input through the first pads and the input data signal input through the second pads to the banks; and a second bus for transferring the output data signal output from the banks to the second pads.
20. The semiconductor memory device of claim 19, wherein, during the core test mode, the test IO control unit decodes the test signal to generate a write command and a read command, transfers the input data signal from the second pads to the first bus in response to the write command, and transfers the output data signal from the second bus to the second pads in response to the read command.
21. The semiconductor memory device of claim 19, wherein the test IO control unit includes: a command decoder for decoding the test signal input through the first pads to generate a write command and a read command, and buffering the input data signal input through the second pads in response to the mode register mode enable signal; a demultiplexer for transferring the buffered input data signal to the first bus in response to the write command; and a multiplexer for receiving the output data signal from the second bus to output the output data signal to the second pads in response to the read command.
22. The semiconductor memory device of claim 21, wherein the test IO control unit further includes a tri-state buffer for selectively buffering the output data signal output from the multiplexer and bypassing the input data signal input through the second pads to the command decoder, in response to a buffer control signal output from the command decoder.
23. A semiconductor memory device, comprising: a mode setting unit for generating a mode setting signal in response to a mode register enable signal input through a plurality of first pads in parallel during a core test mode; a clock generating unit for receiving an external clock signal and generating first and second internal clock signals in response to the mode setting signal; and a test inputoutput (IO) control unit for controlling an input and output of an inputoutput (IO) data signal through a plurality of second pads during the core test mode in synchronization with the first and second internal clock signals.
24. The semiconductor memory device of claim 23, wherein the mode setting signal determines a data transfer mode of the IO data signal which is input and output through the second pads.
25. The semiconductor memory device of claim 24, wherein the first and second internal clock signals synchronize command signals, address signals, and the IO data signal has a data transfer rate corresponding to the data transfer mode.
26. The semiconductor memory device of claim 23, wherein the first internal clock signal is used as a reference clock for the command signals and the address signals generated and used during the core test mode.
27. The semiconductor memory device of claim 23, wherein the second internal clock signal is used as a reference clock of the IO data signal input and output through the second pads during the core test mode.
28. The semiconductor memory device of claim 24, wherein the first internal clock signal has substantially the same waveform regardless of the data transfer modes.
29. The semiconductor memory device of claim 28, wherein the second internal clock signal has a different waveform according to the data transfer modes.
30. The semiconductor memory device of claim 29, wherein the second internal clock signal has a half period of the first internal clock signal.
31. The semiconductor memory device of claim 30, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising and falling edge of the second internal clock signal.
32. The semiconductor memory device of claim 29, wherein the second internal clock signal has substantially the same period as the first internal clock and a phase shifted by 90 degrees in comparison with the first internal clock signal.
33. The semiconductor memory device of claim 32, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising and falling edge of the first and second internal clock signals.
34. The semiconductor memory device of claim 29, wherein the second internal clock signal maintains one of a logic low level and a logic high level regardless of the first internal clock signal.
35. The semiconductor memory device of claim 34, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising and falling edge of the first internal clock signal.
36. The semiconductor memory device of claim 34, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising or falling edge of the first internal clock signal.
37. The semiconductor memory device of claim 28, wherein the second internal clock signal has substantially the same waveform as the first internal clock signal.
38. The semiconductor memory device of claim 37, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising and falling edge of the second internal clock signal.
39. The semiconductor memory device of claim 37, wherein the test IO control unit inputs and outputs the IO data signal through the second pads in synchronization with every rising or falling edge of the second internal clock signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An optical circuit, comprising:
a multimode interference element having a length; and
first and second waveguides, the first waveguide provided adjacent a first side of the multimode interference element and extending along at least the length of the multimode interference element, the second waveguide provided adjacent a second side of the multimode interference element and extending along at least the length of the multimode interference element,
wherein each of the first and second ends of the first and second waveguides are configured to dissipate light which may be propagating through the first and second waveguides, respectively.
2. The optical circuit of claim 1, wherein the multimode interference element is an optical coupler, an optical splitter, or an optical combiner.
3. The optical circuit of claim 1, wherein the multimode interference element is a multimode interference coupler.
4. The optical circuit of claim 1, wherein the first waveguide is spaced a first distance from the multimode interference element, the first distance being substantially constant along the length of the multimode interference element.
5. The optical circuit of claim 4, wherein the first waveguide includes first and second sides, the first side being adjacent the multimode interference element, the second side of the first waveguide being nonparallel to the first side of the first waveguide.
6. The optical circuit of claim 4, wherein the second waveguide is spaced a second distance from the multimode interference element, the second distance being substantially constant along the length of the multimode interference element.
7. The optical circuit of claim 6, wherein the multimode interference element has a width, the first and second distances being selected such that the first and second waveguides provide sufficient loading during the fabrication process to maintain the width of the multimode interference element within a deviation value.
8. The optical circuit of claim 7, wherein the deviation value associated with the width of the multimode interference element is a first deviation value, a second deviation value being associated with the length of the multimode interference element, such that the first deviation value is about 3% of the second deviation value.
9. The optical circuit of claim 1, wherein the first waveguide includes a tapered portion, such that a width of the first waveguide decreases from a point along the first waveguide to the first end of the first waveguide.
10. The optical circuit of claim 1, wherein the first waveguide includes a first end portion which terminates in the first end of the first waveguide, the first end portion including a curved portion.
11. The optical circuit of claim 10, wherein the curved portion is configured such that the first end is spaced from the multimode interference element a distance which is greater than the first distance.
12. The optical circuit of claim 1, wherein the light is dissipated into the substrate.
13. An optical circuit, comprising:
first, second, and third optical couplers, each having first and second inputs and first and second outputs and a length, the first input of the third optical coupler configured to receive light from the first output of the first optical coupler, the second input of the third optical coupler configured to receive light from the first output of the second optical coupler;
a first waveguide coupled to the second output of the first optical coupler, the first waveguide provided spaced from a first side of the third optical coupler a first distance, the first waveguide extending along at least the length of the third optical coupler;
a second waveguide coupled to the second output of the second optical coupler, the second waveguide provided spaced from a second side of the third optical coupler a second distance, the second waveguide extending along at least the length of the third optical coupler;
a first dummy waveguide provided spaced from a first side of the first optical coupler a third distance, the first dummy waveguide extending along at least the length of the first optical coupler;
a second dummy waveguide provided spaced from a first side of the second optical coupler a fourth distance, the second dummy waveguide extending along at least the length of the second optical coupler,
wherein the first, second, third, and fourth distances are substantially the same.
14. The optical circuit of claim 13, wherein each of the first and second dummy waveguides have first and second end portions, each of the first end portions of each of the first and second waveguides being configured to dissipate a portion of light propagating in the first and second waveguides, respectively.
15. The optical circuit of claim 13, wherein each of the first, second, and third optical couplers is a multimode interference coupler.
16. The optical circuit of claim 13, wherein the first dummy waveguide includes first and second sides, the first side adjacent the first optical coupler being nonparallel with respect to the second side.
17. The optical circuit of claim 13, wherein the third optical coupler includes a width, the first and second distances being selected such that the first and second waveguides provide sufficient loading during the fabrication process to maintain the width of the third optical coupler within a deviation value.
18. The optical circuit of claim 17, wherein the deviation value associated with the width of the third optical coupler is a first deviation value, a second deviation value being associated with the length of the third optical coupler, such that the first deviation value is about 3% of the second deviation value.
19. The optical circuit of claim 13, wherein the first waveguide includes a first end, the first end of the first waveguide configured to have a tapered portion, such that a width of the first and second waveguide decreases from a point along the first waveguide to the first end of the first waveguide.
19. The optical circuit of claim 13, wherein the first waveguide includes a first end portion which terminates in the first end of the first waveguide, the first end portion including a curved portion.
20. The optical circuit of claim 19, wherein the curved portion is configured such that the first end of the first waveguide is spaced from the first optical coupler a distance which is greater than the first distance.
21. The optical circuit of claim 13, wherein the first and second optical couplers are spaced a fifth distance, the first optical including a width, the third and fifth distances being selected such that the first dummy waveguide and the second optical coupler provide sufficient loading during the fabrication process to maintain the width of the first optical coupler within a deviation value.
22. The optical circuit of claim 21, wherein the third and fifth distances are substantially the same.
23. The optical circuit of claim 21, wherein the deviation value associated with the width of the first optical coupler is a first deviation value, a second deviation value being associated with the length of the first optical coupler, such that the first deviation value is about 3% of the second deviation value.
24. The optical circuit of claim 13, wherein the first and second optical couplers are spaced a fifth distance, the second optical coupler including a width, the fourth and fifth distances being selected such that the second dummy waveguide and the first optical coupler provide sufficient loading during the fabrication process to maintain the width of the second optical coupler within a deviation value.
25. The optical circuit of claim 24, wherein the fourth and fifth distances are substantially the same.
26. The optical circuit of claim 24, wherein the deviation value associated with the width of second optical coupler is a first deviation value, a second deviation value being associated with the length of the second optical coupler, such that the first deviation value is about 3% of the second deviation value.
27. The optical circuit of claim 13, wherein the first dummy waveguide includes a first end, the first end of the first dummy waveguide configured to have a tapered portion, such that a width of the first dummy waveguide decreases from a point along the first dummy waveguide to the first end of the first waveguide.
28. The optical circuit of claim 13, wherein the first dummy waveguide includes a first end and a first end portion which terminates in the first end of the first dummy waveguide, the first end portion including a curved portion.
29. The optical circuit of claim 28, wherein the curved portion is configured such that the first end of the first dummy waveguide is spaced from the first optical coupler a distance which is greater than the third distance.
30. The optical circuit of claim 28, wherein the curved portion is configured to dissipate a portion of light propagating in the first dummy waveguide.
31. The optical circuit of claim 30, wherein the light is dissipated into the substrate.