1. A semiconductor device comprising:
a memory set comprising a plurality of memory cells;
a comparison circuit electrically connected to the memory set; and
a control portion electrically connected to the memory set,
wherein each of the memory cells includes a first storage portion, a second storage portion, and a data transfer portion,
wherein the first storage portion is configured to store 1-bit data input from the control portion,
wherein the first storage portion is configured to output the 1-bit data to the comparison circuit,
wherein the first storage portion is configured to output the 1-bit data to the data transfer portion,
wherein the data transfer portion is configured to transfer the 1-bit data to the second storage portion, and
wherein the second storage portion is configured to store the 1-bit data and transfer the 1-bit data to the first storage portion.
2. The semiconductor device according to claim 1,
wherein the comparison circuit is configured to detect whether first address data included in the 1-bit data matches second address data input from a CPU, and
wherein when the first address data and the second address data do not match each other, the second storage portion transfers the 1-bit data to the first storage portion and the memory set outputs the 1-bit data to the comparison circuit.
3. The semiconductor device according to claim 1,
wherein the first storage portion is electrically connected to the data transfer portion through a first transistor,
wherein the data transfer portion is electrically connected to the second storage portion through a second transistor, and
wherein the second storage portion is electrically connected to the first storage portion through a third transistor.
4. The semiconductor device according to claim 3,
wherein the first storage portion transfers the 1-bit data to the data transfer portion when the first transistor is on and the data transfer portion stores the 1-bit data when the first transistor is off,
wherein the data transfer portion transfers the 1-bit data to the second storage portion when the second transistor is on and the second storage portion stores the 1-bit data when the second transistor is off, and
wherein the second storage portion transfers the 1-bit data to the first storage portion when the third transistor is on.
5. The semiconductor device according to claim 3,
wherein the first storage portion includes two inverters which are connected to each other to form a ring,
wherein the data transfer portion includes a first capacitor having a pair of electrodes one of which is grounded,
wherein the second storage portion includes a second capacitor having a pair of electrodes one of which is grounded,
wherein the first storage portion is connected to the other electrode of the first capacitor through the first transistor,
wherein the other electrode of the first capacitor and the other electrode of the second capacitor are connected to each other through the second transistor, and
wherein the other electrode of the second capacitor is connected to the first storage portion through an inverter and the third transistor.
6. The semiconductor device according to claim 1,
wherein the plurality of memory cells is configured to form a line.
7. The semiconductor device according to claim 1,
wherein the comparison circuit includes a plurality of tag comparison circuits and a date comparison circuit.
8. The semiconductor device according to claim 3,
wherein a leakage current in an off state per micrometer of a channel width of at least one of the first transistor and the second transistor is lower than or equal to 1\xd710\u221218 A.
9. The semiconductor device according to claim 3,
wherein at least one of the first transistor and the second transistor includes an oxide semiconductor.
10. A cache memory comprising the semiconductor device according to claim 1.
11. An electronic device comprising the cache memory according to claim 10.
12. A semiconductor device comprising:
a memory set comprising a plurality of lines, each of the lines including a plurality of memory cells;
a comparison circuit electrically connected to the memory set; and
a control portion electrically connected to the memory set,
wherein the memory set is configured to select one of the lines specified by the control portion,
wherein each of the memory cells includes a first storage portion, a second storage portion, and a data transfer portion,
wherein the first storage portion is configured to store 1-bit data input from the control portion,
wherein the first storage portion is configured to output the 1-bit data to the comparison circuit,
wherein the first storage portion is configured to output the 1-bit data to the data transfer portion,
wherein the data transfer portion is configured to transfer the 1-bit data to the second storage portion, and
wherein the second storage portion is configured to store the 1-bit data and transfer the 1-bit data to the first storage portion.
13. The semiconductor device according to claim 12,
wherein the comparison circuit is configured to detect whether first address data included in the 1-bit data matches second address data input from a CPU, and
wherein when the first address data and the second address data do not match each other, the second storage portion transfers the 1-bit data to the first storage portion and the memory set outputs the 1-bit data to the comparison circuit.
14. The semiconductor device according to claim 12,
wherein the first storage portion is electrically connected to the data transfer portion through a first transistor,
wherein the data transfer portion is electrically connected to the second storage portion through a second transistor, and
wherein the second storage portion is electrically connected to the first storage portion through a third transistor.
15. The semiconductor device according to claim 14,
wherein the first storage portion transfers the 1-bit data to the data transfer portion when the first transistor is on and the data transfer portion stores the 1-bit data when the first transistor is off,
wherein the data transfer portion transfers the 1-bit data to the second storage portion when the second transistor is on and the second storage portion stores the 1-bit data when the second transistor is off, and
wherein the second storage portion transfers the 1-bit data to the first storage portion when the third transistor is on.
16. The semiconductor device according to claim 14,
wherein the first storage portion includes two inverters which are connected to each other to form a ring,
wherein the data transfer portion includes a first capacitor having a pair of electrodes one of which is grounded,
wherein the second storage portion includes a second capacitor having a pair of electrodes one of which is grounded,
wherein the first storage portion is connected to the other electrode of the first capacitor through the first transistor,
wherein the other electrode of the first capacitor and the other electrode of the second capacitor are connected to each other through the second transistor, and
wherein the other electrode of the second capacitor is connected to the first storage portion through an inverter and the third transistor.
17. The semiconductor device according to claim 12,
wherein the comparison circuit includes a plurality of tag comparison circuits and a date comparison circuit.
18. The semiconductor device according to claim 14,
wherein a leakage current in an off state per micrometer of a channel width of at least one of the first transistor and the second transistor is lower than or equal to 1\xd710\u221218 A.
19. The semiconductor device according to claim 14,
wherein at least one of the first transistor and the second transistor includes an oxide semiconductor.
20. A cache memory comprising the semiconductor device according to claim 12.
21. An electronic device comprising the cache memory according to claim 20.
22. A method for driving a semiconductor device, the semiconductor device comprising a memory set including a plurality of lines, a control portion, and a comparison circuit, wherein each of the lines includes a plurality of memory cells, and wherein each of the memory cells includes a first storage portion, a second storage portion and a data transfer portion,
the method comprising the steps of:
selecting one of the lines specified by the control portion;
outputting, to the comparison circuit, a first data group output from the first storage portions of the plurality of the memory cells included in the one of the lines;
comparing first address data included in the first data group with second address data input from a CPU by the comparison circuit; and
detecting whether the first address data matches the second address data.
23. The method for driving the semiconductor device according to claim 22,
wherein the first storage portion is electrically connected to the data transfer portion through a first transistor,
wherein the data transfer portion is electrically connected to the second storage portion through a second transistor, and
wherein the second storage portion is electrically connected to the first storage portion through a third transistor.
24. The method for driving the semiconductor device according to claim 23,
wherein the first storage portion transfers the 1-bit data to the data transfer portion when the first transistor is on and the data transfer portion stores the 1-bit data when the first transistor is off,
wherein the data transfer portion transfers the 1-bit data to the second storage portion when the second transistor is on and the second storage portion stores the 1-bit data when the second transistor is off, and
wherein the second storage portion outputs the 1-bit data to the first storage portion when the third transistor is on.
25. The method for driving the semiconductor device according to claim 23,
wherein the first storage portion includes two inverters which are connected to each other to form a ring,
wherein the data transfer portion includes a first capacitor having a pair of electrodes one of which is grounded,
wherein the second storage portion includes a second capacitor having a pair of electrodes one of which is grounded,
wherein the first storage portion is connected to the other electrode of the first capacitor through the first transistor,
wherein the other electrode of the first capacitor and the other electrode of the second capacitor are connected to each other through the second transistor, and
wherein the other electrode of the second capacitor is connected to the first storage portion through an inverter and the third transistor.
26. The method for driving the semiconductor device according to claim 22,
wherein the comparison circuit includes a plurality of tag comparison circuits and a date comparison circuit.
27. The method for driving the semiconductor device according to claim 23,
wherein a leakage current in an off state per micrometer of a channel width of at least one of the first transistor and the second transistor is lower than or equal to 1\xd710\u221218 A.
28. The method for driving the semiconductor device according to claim 23,
wherein at least one of the first transistor and the second transistor includes an oxide semiconductor.
29. A cache memory comprising the semiconductor device according to claim 22.
30. A method for driving a semiconductor device, the semiconductor device comprising a memory set including a plurality of lines, a control portion, and a comparison circuit, wherein each of the lines includes a plurality of memory cells, and wherein each of the memory cells includes a first storage portion, a second storage portion and a data transfer portion,
the method comprising the steps of:
selecting one of the lines specified by the control portion;
outputting, to the comparison circuit, a first data group output from the first storage portions of the plurality of the memory cells included in the one of the lines;
comparing first address data included in the first data group with second address data input from a CPU by the comparison circuit to detect whether the first address data matches the second address data;
outputting, from the comparison circuit to the CPU, a cache hit signal and main data included in the first data group, when the first address data matches the second address data; and
outputting data of the second storage portion to the first storage portion and outputting, from the memory set to the comparison circuit, a second data group output from the first storage portions in the plurality of memory cells, when the first address data does not match the second address data.
31. The method for driving the semiconductor device according to claim 30,
wherein the first storage portion is electrically connected to the data transfer portion through a first transistor,
wherein the data transfer portion is electrically connected to the second storage portion through a second transistor, and
wherein the second storage portion is electrically connected to the first storage portion through a third transistor.
32. The method for driving the semiconductor device according to claim 31,
wherein the first storage portion transfers the 1-bit data to the data transfer portion when the first transistor is on and the data transfer portion stores the 1-bit data when the first transistor is off,
wherein the data transfer portion transfers the 1-bit data to the second storage portion when the second transistor is on and the second storage portion stores the 1-bit data when the second transistor is off, and
wherein the second storage portion outputs the 1-bit data to the first storage portion when the third transistor is on.
33. The method for driving the semiconductor device according to claim 31,
wherein the first storage portion includes two inverters which are connected to each other to form a ring,
wherein the data transfer portion includes a first capacitor having a pair of electrodes one of which is grounded,
wherein the second storage portion includes a second capacitor having a pair of electrodes one of which is grounded,
wherein the first storage portion is connected to the other electrode of the first capacitor through the first transistor,
wherein the other electrode of the first capacitor and the other electrode of the second capacitor are connected to each other through the second transistor, and
wherein the other electrode of the second capacitor is connected to the first storage portion through an inverter and the third transistor.
34. The method for driving the semiconductor device according to claim 30,
wherein the comparison circuit includes a plurality of tag comparison circuits and a date comparison circuit.
35. The method for driving the semiconductor device according to claim 31,
wherein a leakage current in an off state per micrometer of a channel width of at least one of the first transistor and the second transistor is lower than or equal to 1\xd710\u221218 A.
36. The method for driving the semiconductor device according to claim 31,
wherein at least one of the first transistor and the second transistor includes an oxide semiconductor.
37. A cache memory comprising the semiconductor device according to claim 30.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for treating a patient suffering from non-coronary microvascular disease comprising:
a) selecting a patient suffering from, or at risk of suffering from, non-coronary microvascular disease, and
b) administering to that patient an effective amount of ranolazine.
2. The method of claim 1, wherein the patient is not suffering from diabetes.
3. The method of claim 1, wherein the patient is suffering from at least one condition selected from the group consisting of hypertension, incipient diabetes, and metabolic syndrome.
4. The method of claim 1, wherein the non-coronary microvascular disease is manifested in the eye.
5. The method of claim 1, wherein the non-coronary microvascular disease is manifested in the brain.
6. The method of claim 1, wherein the non-coronary microvascular disease is manifested in the kidney.
7. The method of claim 1, wherein the non-coronary microvascular disease is manifested in the liver.
8. The method of claim 1, wherein the non-coronary microvascular disease is manifested as Restless Legs Syndrome.
9. The method of claim 1, wherein the ranolazine is administered to the patient as an oral dose.
10. The method of claim 9, where in the oral dose is a sustained release tablet.
11. The method of claim 9, wherein the sustained release tablet comprises at least 50% by weight ranolazine, a pH dependent binder, and a pH independent binder.
12. The method of claim 11, wherein the sustained release table comprises at least 50% by weight ranolazine, from about 5 to about 12.5% by weight methacrylic acid copolymer, from about 1 to about 3% by weight of hydroxypropyl methylcellulose, microcrystalline cellulose, sodium hydroxide, and magnesium stearate.
13. A method for reducing non-cardiovascular ischemia in a patient at risk of non-cardiovascular ischemia which method comprises administering ranolazine to said patient.
14. The method of claim 13, wherein said ischemia is selected from the group consisting of cerebral ischemia, renal ischemia, and ischemia associated with organ transplant.