1. A submersible shellfish farm comprising at least one line of cables bearing spaced culture ropes, said at least one line being suspended horizontally from two end floats which support said at least one line in association with intermediate support buoys positioned in relation to said at least one line of cables to maintain said at least one line of cables in a non-catenary manner, and said at least one line is further anchored by concrete dead weights positioned at each end of the at least one line, wherein the at least one line of cables is submersible and is elevated from a sea floor while guided by vertical movement of the two end floats when the two end floats are submerged, said two end floats being submerged or raised based on inner volume of said floats being variable by filling or draining of said inner volume of water or air and said end floats being connected to a surface buoy including an air intake valve, and said two end floats are connected to the concrete dead weights by an anchoring system which is constructed and arranged to create a vertical thrust on said at least one line of cables to tension and maintain tension on the at least one line of cables.
2. A submersible shellfish farm in accordance with claim 1, wherein said anchoring system comprises at least one end buoy submerged and arranged so as to use uplift thrust of said end buoy to pull at each of said end floats to which said end floats are respectively connected by means of tensioning cables and pulleys fixed to said concrete dead weights.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic system, comprising:
a processor; and
a non-volatile memory device coupled to the processor, wherein the non-volatile memory device comprises:
an array of non-volatile floating-gate memory cells arranged in rows and columns; and
control circuitry for controlling access to the array of memory cells;
wherein the array of memory cells comprises:
a first column of memory cells having a first sourcedrain region and a second sourcedrain region laterally spaced apart in a first well associated with the first column, wherein the first well associated with the first column has a first conductivity type and the first and second sourcedrain regions have a second conductivity type opposite the first conductivity type; and
a second column of memory cells having a first sourcedrain region and a second sourcedrain region laterally spaced apart in a first well associated with the second column, wherein the first well associated with the second column has the first conductivity type and the first and second sourcedrain regions have the second conductivity type opposite the first conductivity type;
wherein the first column of memory cells and the second column of memory cells are isolated from each other by an interposing dielectric material and by an underlying second well having the second conductivity type;
wherein the first and second sourcedrain regions of the first column of memory cells are each a continuous structure that spans the first column of memory cells; and
wherein the first and second sourcedrain regions of the second column of memory cells are each a continuous structure that spans the second column of memory cells.
2. The electronic system of claim 1, wherein one or more of the first and second sourcedrain regions of the array of the non-volatile memory device is in contact with the interposing dielectric material.
3. The electronic system of claim 1, wherein the array of the non-volatile memory device further comprises additional columns of memory cells isolated from other columns of memory cells by interposing dielectric material and by the underlying second well.
4. The electronic system of claim 1, wherein the first conductivity type is a p-type conductivity and the second conductivity type is an n-type conductivity.
5. An electronic system, comprising:
a processor; and
a non-volatile memory device coupled to the processor, wherein the non-volatile memory device comprises:
an array of floating-gate field-effect transistors, the array comprising:
two or more columns of the floating-gate field-effect transistors, each field-effect transistor of a column sharing a first sourcedrain region and a second sourcedrain region with other field-effect transistors of that column;
wherein the first and second sourcedrain regions of a column are contained in a first well having a first conductivity type;
wherein the first well for each column is isolated from first wells of other columns; and
wherein the first and second sourcedrain regions of each column are each a continuous structure that spans the respective column.
6. The electronic system of claim 5, wherein the first wells of the array of floating-gate field-effect transistors are isolated from each other in part by a second well having a second conductivity type different from the first conductivity type.
7. The electronic system of claim 6, wherein the first wells of the array of floating-gate field-effect transistors are isolated from each other by isolation trenches interposed between adjacent first wells and by the second well.
8. The electronic system of claim 6, wherein the second conductivity type is opposite the first conductivity type.
9. The electronic system of claim 8, wherein the first conductivity type is a p-type conductivity and the second conductivity type is an n-type conductivity.
10. An electronic system, comprising:
a processor; and
a non-volatile memory device coupled to the processor, wherein the non-volatile memory device comprises:
an array of non-volatile floating-gate memory cells arranged in rows and columns;
wherein each column of memory cells shares a source and a drain, the source and drain for a column of memory cells being contained in a first well associated with that column of memory cells;
wherein the source of each column of memory cells is a continuous structure that spans the respective column of memory cells;
wherein the drain of each column of memory cells is a continuous structure that spans the respective column of memory cells;
wherein the first well associated with each column of memory cells is isolated from other first wells of other columns of memory cells by a means for insulation; and
wherein each first well is overlying a second well in a many-to-one relationship.
11. The electronic system of claim 10, wherein each first well has a first conductivity type, and wherein the second well has a second conductivity type different than the first conductivity type.
12. The electronic system of claim 11, wherein the first conductivity type is a p-type conductivity and the second conductivity type is an n-type conductivity.
13. The electronic system of claim 11, wherein the first well is isolated from each other first well by one or more means for insulation interposed between adjacent first wells and by the second well.
14. The electronic system of claim 13, wherein the second well is underlying and in contact with the one or more means for insulation.
15. An electronic system, comprising:
a processor; and
a non-volatile memory device coupled to the processor, wherein the non-volatile memory device comprises:
an array of non-volatile floating-gate memory cells arranged in rows and columns; and
control circuitry for controlling access to the array of memory cells;
wherein the array of memory cells comprises:
a first column of memory cells having a first sourcedrain region and a second sourcedrain region laterally spaced apart in a first well associated with the first column, wherein the first well associated with the first column has a first conductivity type and the first and second sourcedrain regions have a second conductivity type opposite the first conductivity type; and
a second column of memory cells having a first sourcedrain region and a second sourcedrain region laterally spaced apart in a first well associated with the second column, wherein the first well associated with the second column has the first conductivity type and the first and second sourcedrain regions have the second conductivity type opposite the first conductivity type;
wherein the first column of memory cells and the second column of memory cells are isolated from each other by an interposing dielectric material and by an underlying second well having the second conductivity type;
wherein the first and second sourcedrain regions of the first column of memory cells are each a continuous structure that spans the first column of memory cells;
wherein the first and second sourcedrain regions of the second column of memory cells are each a continuous structure that spans the second column of memory cells;
wherein one or more of the first and second sourcedrain regions of the array of the non-volatile memory device is in contact with the interposing dielectric material; and
wherein the first conductivity type is a p-type conductivity and the second conductivity type is an n-type conductivity.
16. The electronic system of claim 15, wherein the array of the non-volatile memory device further comprises additional columns of memory cells isolated from other columns of memory cells by interposing dielectric material and by the underlying second well.
17. An electronic system, comprising:
a processor; and
a non-volatile memory device coupled to the processor, wherein the non-volatile memory device comprises:
an array of floating-gate field-effect transistors, the array comprising:
two or more columns of the floating-gate field-effect transistors, each field-effect transistor of a column sharing a first sourcedrain region and a second sourcedrain region with other field-effect transistors of that column;
wherein the first and second sourcedrain regions of a column are contained in a first well having a first conductivity type;
wherein the first and second sourcedrain regions of each column are each a continuous structure that spans the respective column;
wherein the first well for each column is isolated from first wells of other columns;
wherein the first wells of the array of floating-gate field-effect transistors are isolated from each other by isolation trenches interposed between adjacent first wells and by a second well having a second conductivity type different from the first conductivity type; and
wherein the second conductivity type is opposite the first conductivity type.
18. The electronic system of claim 17, wherein the first conductivity type is a p-type conductivity and the second conductivity type is an n-type conductivity.
19. An electronic system, comprising:
a processor; and
a non-volatile memory device coupled to the processor, wherein the non-volatile memory device comprises:
an array of non-volatile floating-gate memory cells arranged in rows and columns;
wherein each column of memory cells shares a source and a drain, the source and drain for a column of memory cells being contained in a first well associated with that column of memory cells;
wherein the source of each column of memory cells is a continuous structure that spans the respective column of memory cells;
wherein the drain of each column of memory cells is a continuous structure that spans the respective column of memory cells;
wherein the first well associated with each column of memory cells is isolated from other first wells of other columns of memory cells by a means for insulation;
wherein each first well is overlying a second well in a many-to-one relationship;
wherein each first well has a p-type conductivity, and wherein the second well has an n-type conductivity; and
wherein the first well is isolated from each other first well by one or more means for insulation interposed between adjacent first wells and by the second well.
20. The electronic system of claim 19, wherein the second well is underlying and in contact with the one or more means for insulation.