1. An apparatus for transferring data between components in a computer system, comprising:
a proximity IO switch configured to transfer data between the components in the computer system;
wherein the proximity IO switch is comprised of multiple switch chips which are coupled together and are configured to collectively function as a switch; and
wherein the multiple switch chips in the proximity IO switch are configured to communicate with the components in the computer system through capacitive andor conventional non-capacitive communication mechanisms.
2. The apparatus of claim 1, wherein the multiple switch chips are configured to communicate with each other through capacitive coupling, whereby the multiple switch chips can communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms.
3. The apparatus of claim 1, wherein the multiple switch chips are alternately oriented face-up and face-down in an array, so that capacitive communication surfaces on active faces of the multiple switch chips overlap, thereby facilitating capacitive communication between the multiple switch chips.
4. The apparatus of claim 3, wherein the array of switch chips is two-dimensional so that corners of alternately oriented (face-up and face-down) switch chips overlap.
5. The apparatus of claim 4, the multiple switch chips in the array are permanently or removably attached to one or more Micro-Electro-Mechanical System (MEMS) jig-plates, which are fabricated to accommodate the multiple switch chips.
6. The apparatus of claim 4, wherein switch chips on the perimeter of the two-dimensional array of switch chips are configured to communicate with the components in the computer system through the conventional non-capacitive communication mechanisms.
7. The apparatus of claim 1, wherein the conventional non-capacitive communication mechanisms can include:
electrically conductive connections; and
optical communication mechanisms.
8. The apparatus of claim 1, wherein the components in the computer system include:
processors;
memories;
peripheral devices; and
network interfaces.
9. A computer system including a proximity IO switch for transferring data, comprising:
a processor;
a memory;
a proximity IO switch configured to transfer data between the components in the computer system, wherein the components include the processor and the memory;
wherein the proximity IO switch is comprised of multiple switch chips which are coupled together and are configured to collectively function as a switch; and
wherein the multiple switch chips in the proximity IO switch are configured to communicate with the components in the computer system through capacitive andor conventional non-capacitive communication mechanisms.
10. The computer system of claim 9, wherein the multiple switch chips are configured to communicate with each other through capacitive coupling, whereby the multiple switch chips can communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms.
11. The computer system of claim 9, wherein the multiple switch chips are alternately oriented face-up and face-down in an array, so that capacitive communication surfaces on active faces of the multiple switch chips overlap, thereby facilitating capacitive communication between the multiple switch chips.
12. The computer system of claim 11, wherein the array of switch chips is two-dimensional so that corners of alternately oriented (face-up and face-down) switch chips overlap.
13. The computer system of claim 12, wherein the multiple switch chips in the array are permanently or removably attached to one or more Micro-Electro-Mechanical System (MEMS) jig-plates, which are fabricated to accommodate the multiple switch chips.
14. The computer system of claim 12, wherein switch chips on the perimeter of the two-dimensional array of switch chips are configured to communicate with the components in the computer system through the conventional non-capacitive communication mechanisms.
15. The computer system of claim 9, wherein the conventional non-capacitive communication mechanisms include:
electrically conductive connections; and
optical communication mechanisms.
16. The computer system of claim 9, wherein the components in the computer system include:
processors;
memories;
peripheral devices; and
network interfaces.
17. A method for transferring data between components in a computer system, comprising:
transferring data between the components in the computer system through a proximity IO switch;
wherein the proximity IO switch is comprised of multiple switch chips which are coupled together and are configured to collectively function as a switch; and
wherein the multiple switch chips in the proximity IO switch communicate with the components in the computer system through capacitive andor conventional non-capacitive communication mechanisms.
18. The method of claim 17, wherein the multiple switch chips communicate with each other through capacitive coupling, whereby the multiple switch chips can communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms.
19. The method of claim 17, wherein the multiple switch chips are alternately oriented face-up and face-down in an array, so that capacitive communication surfaces on active faces of the multiple switch chips overlap, thereby facilitating capacitive communication between the multiple switch chips.
20. The method of claim 19, wherein the array of switch chips is two-dimensional so that corners of alternately oriented (face-up and face-down) switch chips overlap.
21. The method of claim 20, wherein the multiple switch chips in the array are permanently or removably attached to one or more Micro-Electro-Mechanical System (MEMS) jig-plates, which are fabricated to accommodate the multiple switch chips.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A storage controller comprising:
an error information management section configured to manage error information in a plurality of addresses of a memory; and
a refresh object determination section configured to determine a refresh object address in the memory based on the error information.
2. The storage controller according to claim 1, wherein
the error information management section manages, as the error information, an address where errors are detected in association with the number of detected errors, and
the refresh object determination section determines the address associated with the number of errors as the refresh object address, based on the number of errors.
3. The storage controller according to claim 2, wherein the error information management section determines whether the error information is excluded from management objects, based on the number of errors.
4. The storage controller according to claim 2, wherein
the error information management section further manages, as the error information, the number of reading times in association with the address, and
the refresh object determination section determines the address associated with the number of reading times as the refresh object address, based on the number of reading times.
5. The storage controller according to claim 1, wherein when errors occur in the memory, the error information management section determines whether the error information is excluded from management objects, based on a condition specified in advance.
6. The storage controller according to claim 1, wherein
the error information management section manages, as the error information, a physical address of the memory where errors are detected in association with the number of detected errors, and
the refresh object determination section determines the physical address associated with the number of errors as the refresh object address, based on the number of errors.
7. The storage controller according to claim 1, further comprising an address conversion section configured to convert a logical address into a physical address of the memory, the logical address being used in an access command from a host computer to the memory, wherein
the error information management section manages, as the error information, the logical address of the memory where errors are detected in association with the number of detected errors, and
the refresh object determination section selects the logical address associated with the number of errors based on the number of errors, and converts the logical address into the physical address with use of the address conversion section, to determine the physical address as the refresh object address.
8. The storage controller according to claim 1, wherein the error information management section holds data stored in each of the addresses in the memory, and uses the data in accessing the address of the memory, the data being associated with the error information.
9. The storage controller according to claim 8, wherein the error information management section holds an error correcting code in addition to the data.
10. The storage controller according to claim 8, wherein the error information management section holds the data only when the number of errors included in the error information satisfies a predetermined condition.
11. The storage controller according to claim 1, wherein the error information management section notifies a host computer of the error information when receiving an acquisition command of the error information from the host computer.
12. A storage device comprising:
a memory;
an error information management section configured to manage error information in a plurality of addresses of the memory; and
a refresh object determination section configured to determine a refresh object address in the memory, based on the error information.
13. An information processing system comprising:
a memory;
a host computer configured to issue an access command with respect to the memory;
an error information management section configured to manage error information in a plurality of addresses of the memory; and
a refresh object determination section configured to determine a refresh object address in the memory, based on the error information.
14. The information processing system according to claim 13, wherein the host computer includes the error information management section and the refresh object determination section.
15. A storage control method comprising:
managing error information in a plurality of addresses of a memory; and
determining a refresh object address in the memory, based on the error information.