What is claimed is:
1. A method of testing a to-be-tested circuit having a redundancy circuit, comprising:
an initial test condition testing step of performing a logical test of the to-be-tested circuit under a first test condition to obtain first fault information and judging, according to the first fault information, whether or not the repair of the faulty portion of the to-be-tested circuit by the redundancy circuit is possible; and
a confirmation step including a first step of performing a logical test, which is the same as the logical test performed in the initial test condition testing step, for the to-be-tested circuit under a second test condition different from the first test condition to obtain second fault information, in a case where it is judged that the repair of the faulty portion of the to-be-tested circuit is possible, and a second step of comparing the first fault information with the second fault information to obtain a comparison result which indicates whether the to-be-tested circuit is correctly operable under each of the first test condition and the second test condition.
2. A testing method according to claim 1, further comprising:
a test condition change giving step of giving a change to the first test condition to change a test condition, under which the to-be-tested circuit is tested, to obtain the second test condition.
3. A testing method according to claim 2, wherein the test condition change giving step includes
a step of performing a pseudo-logical test for the to-be-tested circuit or a circuit arranged in a periphery of the to-be-tested circuit to change the test condition.
4. A testing method according to claim 3, wherein the test condition change giving step further includes
a step of judging whether a test condition, under which the to-be-tested circuit is tested, reaches the second test condition, wherein
the step of performing the pseudo-logical test is repeated in a case where it is judged in the judging step that the test condition does not reach the second test condition.
5. A testing method according to claim 1, wherein the first and second steps of the confirming step are repeated prescribed times with a change given to the second test condition, wherein the confirming step further includes a step of confirming a correct operation of the to-be-tested circuit according to a comparison result obtained every time the second step is performed.
6. A testing method according to claim 5, wherein the first and second steps of the confirming step are repeated until the second test condition reaches a predetermined test condition.
7. A testing method according to claim 1, wherein the first test condition corresponds to a first temperature of the to-be-tested circuit, and the second test condition corresponds to a second temperature of the to-be-tested circuit.
8. A testing method according to claim 1, wherein the first test condition corresponds to a first power supply voltage applied to the to-be-tested circuit, and the second test condition corresponds to a second power supply voltage applied to the to-be-tested circuit.
9. A test apparatus of a to-be-tested circuit, comprising:
a register for storing first fault information obtained by performing a logical test of the to-be-tested circuit under a first test condition; and
a test circuit for judging according to the first fault information stored in the register whether or not a faulty portion exists in the to-be-tested circuit, judging according to the first fault information whether or not the repair of the faulty portion of the to-be-tested circuit is possible in a case where the faulty portion exists in the to-be-tested circuit, performing a logical test, which is the same as the logical test performed under the first test condition, for the to-be-tested circuit under a second test condition different from the first test condition to obtain second fault information in a case where the repair of the faulty portion of the to-be-tested circuit is possible, and comparing the first fault information with the second fault information to obtain a comparison result which indicates whether the to-be-tested circuit is correctly operable under each of the first test condition and the second test condition.
10. A test apparatus according to claim 9, wherein the test circuit performs a pseudo-logical test for the to-be-tested circuit or a circuit arranged in a periphery of the to-be-tested circuit to give a change to the first test condition.
11. A test apparatus according to claim 10, wherein the test circuit continues the pseudo-logical test until a test condition, under which the to-be-tested circuit is tested, reaches the second test condition.
12. A test apparatus according to claim 9, wherein the test circuit repeatedly performs the logical test, which is the same as the logical test performed under the first test condition, prescribed times with a change given to the second test condition, and performs a comparison of the first fault information with the second fault information obtained every time the logical test is performed, and
the test circuit confirms, according to a comparison result obtained every time the comparison is performed, that the to-be-tested circuit is correctly operable.
13. A test apparatus according to claim 9, wherein the test circuit repeatedly performs the logical test until the second test condition reaches a predetermined test condition.
14. A test apparatus according to claim 9, wherein the first test condition corresponds to a first temperature of the to-be-tested circuit, and the second test condition corresponds to a second temperature of the to-be-tested circuit.
15. A test apparatus according to claim 9, wherein the first test condition corresponds to a first power supply voltage applied to the to-be-tested circuit, and the second test condition corresponds to a second power supply voltage applied to the to-be-tested circuit.
16. A testing method according to claim 1, wherein the first and second steps of the confirming step are performed again with a change given to the second test condition when the comparison result indicates a match, while the first or second step is not performed any more when the comparison result indicates a mismatch.
17. A test apparatus according to claim 9, wherein the test circuit further performs the logical test again with a change given to the second test condition when the comparison result indicates a match, while not performing the logical test any more when the comparison result indicates a mismatch.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system for graphics processing comprising:
a central processing unit to process applicationvideo game program code and a graphics processing unit (GPU) to process graphics commands and generate a series of video frames for the applicationvideo game;
one or more back buffers to store video frames as the video frames are being created in response to the execution of the graphics commands;
a front buffer to receive a video frame for rendering on a display after the video frame has been completed in one of the one or more back buffers, the front buffer outputting the video frame for display one scan line at a time at a designated scan out frequency, a subset of scan lines stored in the front buffer being associated with a vertical blanking interval (VBI); and
a frame processing module to begin copying a newly completed frame from the back buffer to the front buffer before the video data for a prior video frame stored in the front buffer has been fully scanned out.
2. The system as in claim 1 wherein the frame processing module comprises program code for performing the additional operations of:
determining the most recent scan line output from the front buffer; and
copying the completed video frame from the back buffer to the front buffer only if the most recent scan line output from the front buffer is outside of a designated center region of the video frame.
3. The system as in claim 1 wherein the frame processing module comprises program code for performing the additional operations of:
executing a video frame mixing operation to combine the newly completed frame with the prior video frame in the front buffer.
4. The system as in claim 3 wherein the mixing operation comprises a cross-fade operation.
5. The system as in claim 3 wherein the mixing operation is a blend operation.
6. The system as in claim 2 wherein, if the current scan line is within the designated center region of the display, the frame processing module waits a period of time until the current scan line has moved outside of the designated center region before copying the newly completed frame from the back buffer to the front buffer.
7. The system as in claim 6 wherein the frame processing module comprises program code for performing the additional operations of:
inserting busy work into a command queue of the GPU based on the period of time to be waited, the amount of busy work approximating the period of time.
8. The system as in claim 7 wherein the busy work comprises a plurality of operations which have no effect on the visual appearance of the frame in the front buffer.
9. The system as in claim 8 wherein the busy work comprises a plurality of invisible triangles.
10. The system as in claim 8 wherein the busy work comprises a series of vertical quads which miss all of the pixel centers.
11. The system as in claim 8 wherein the busy work comprises a series of long polygons with long shaders that perform trivial math.
12. A system for graphics processing comprising:
a central processing unit to process applicationvideo game program code and a graphics processing unit (GPU) to process graphics commands and generate a series of video frames for the applicationvideo game;
one or more back buffers to store video frames as the video frames are being created in response to the execution of the graphics commands;
a front buffer to receive a video frame for rendering on a display after the video frame has been completed in one of the one or more back buffers, the front buffer outputting the video frame for display one scan line at a time at a designated scan out frequency, a subset of scan lines stored in the front buffer being associated with an interval;
a frame processing module to perform the operations of:
determining a most recent scan line output from the front buffer;
in response to a new frame being completed in one of the back buffers, determining an amount of work remaining in a GPU command queue and, if the amount of work remaining in the command queue would cause the newly completed frame from the back buffer to be copied to the front buffer while a current scan line being output from the front buffer is outside of a designated region of the video frame, then inserting an operation in the command queue, the operation to cause the new frame in the back buffer to be transferred to the front buffer after the work remaining in the command queue is completed.
13. The system as in claim 12 wherein, if the amount of work remaining in the command queue would cause the newly completed frame from the back buffer to be copied to the front buffer while a current scan line being output from the front buffer is within the designated region of the video frame, then submitting busy work to the command queue to ensure that the newly completed frame from the back buffer will be copied to the front buffer while a current scan line being output from the front buffer is outside of the designated region.
14. The system as in claim 12 wherein the interval comprises a vertical blanking interval and wherein the designated region comprises all of the front buffer except for the region occupied by the vertical blanking interval.
15. The system as in claim 12 wherein a first thread creates new frames within the one or more back buffers and a second thread determines a most recent frame output from the front buffer and executes the operation to cause the new frame in the back buffer to be transferred to the front buffer after the work remaining in the command queue is completed.
16. The system as in claim 12 wherein the frame processing module comprises program code for performing the additional operations of:
executing a video frame mixing operation to combine the newly completed frame with the prior video frame in the front buffer.
17. The system as in claim 16 wherein the mixing operation comprises a cross-fade operation.
18. The system as in claim 16 wherein the mixing operation is a blend operation.
19. The system as in claim 13 wherein the busy work comprises a plurality of operations which have no effect on the visual appearance of the frame in the front buffer.
20. The system as in claim 19 wherein the busy work comprises a plurality of invisible triangles.
21. The system as in claim 19 wherein the busy work comprises a series of vertical quads which miss all of the pixel centers.
22. The system as in claim 19 wherein the busy work comprises a series of long polygons with long shaders that perform trivial math.
23. A system for graphics processing comprising:
a central processing unit to process applicationvideo game program code and a graphics processing unit (GPU) to process graphics commands and generate a series of video frames for the applicationvideo game;
one or more back buffers to store video frames as the video frames are being created in response to the execution of the graphics commands;
a front buffer to receive a video frame for rendering on a display after the video frame has been completed in one of the one or more back buffers, the front buffer outputting the video frame for display one scan line at a time at a designated scan out frequency, a subset of scan lines stored in the front buffer being associated with an interval; and
a frame processing module to increase the number of scan lines associated with the interval relative to the number of scan lines not associated with the interval to increase the likelihood that a new frame will be completed in a back buffer and ready for transfer to the front buffer at a time when the subset of scan lines stored in the front buffer being associated with the interval is processed.
24. The system as in claim 23 wherein increasing the number of scan lines associated with the interval relative to the number of scan lines not associated with the interval comprises configuring the front buffer to have a larger size than the size of the back buffer.
25. The system as in claim 24 wherein the front buffer is configured to be two times the size of the back buffer.
26. The system as in claim 23 wherein in response to detecting a draw operation which will cause the new frame in the back buffer to be transferred to the front buffer, the frame processing module determines an amount of work remaining in a GPU command queue and, if the amount of work remaining in the command queue would cause the newly completed frame from the back buffer to be copied to the front buffer while a current scan line being output from the front buffer is outside of the interval, then, then inserting the draw operation in the command queue.
27. The system as in claim 26 wherein, in response to detecting a draw operation which will cause the new frame in the back buffer to be transferred to the front buffer, the frame processing module determines whether the amount of work remaining in the command queue would cause the newly completed frame from the back buffer to be copied to the front buffer while a current scan line being output from the front buffer is outside of the interval, then the frame processing module submits busy work to the command queue to ensure that the newly completed frame from the back buffer will be copied to the front buffer while a current scan line being output from the front buffer is within the interval.
28. The system as in claim 23 wherein a first thread creates new frames within the one or more back buffers and a second thread determines a most recent frame output from the front buffer and executes a draw operation to cause the new frame in the back buffer to be transferred to the front buffer after the current work remaining in the command queue is completed.
29. The system as in claim 27 wherein the busy work comprises a plurality of operations which have no effect on the visual appearance of the frame in the front buffer.
30. The system as in claim 29 wherein the busy work comprises a plurality of invisible triangles.
31. The system as in claim 29 wherein the busy work comprises a series of vertical quads which miss all of the pixel centers.
32. The system as in claim 29 wherein the busy work comprises a series of long polygons with long shaders that perform trivial math.