What is claimed is:
1. An ink ejectability maintenance device for maintaining an ink ejectability of a print head which ejects ink droplets to a recording medium, comprising:
a wiper, which wipes a nozzle formation face of the print head; and
a wiper cleaner formed with a slit, which removes adhesions on the wiper when the wiper passes through the slit.
2. The ink ejectability maintenance device as set forth in claim 1, wherein a width of the slit is substantially identical with a thickness of the wiper.
3. The ink ejectability maintenance device as set forth in claim 1, wherein the wiper and the wiper cleaner change their position in cooperation with each other.
4. The ink ejectability maintenance device as set forth in claim 3, wherein the wiper is movable between a wiping position and a non-wiping position, and passes through the slit while moving from one of the wiping position and the non-wiping position to the other.
5. The ink ejectability maintenance device as set forth in claim 3, wherein the wiper cleaner is pivotably held on the device.
6. The ink ejectability maintenance device as set forth in claim 3, wherein the wiper cleaner is provided with a guide pin which is fitted with a guide groove formed on a wiper holder which holds the wiper.
7. An ink jet printer comprising the ink ejectability maintenance device as set forth in any one of claims 1 to 6.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A computing system comprising:
a processor;
a memory system, that includes at least one DRAM module;
a DRAM controller, wherein the DRAM controller is operable to limit an access rate to the at least one DRAM module so that an average DRAM module power consumption rate is less than or equal to a desired memory power consumption rate; and
a bus that couples the memory system, the processor and the DRAM controller.
2. The system of claim 1, wherein the DRAM controller includes a state machine.
3. The system of claim 1, wherein the access rate is equal to a number of accesses per a current time interval.
4. The system of claim 3, further comprising a power supply for the memory system.
5. The system of claim 4, wherein the length for the current time interval is less than a regulation time constant of the power supply for the memory system.
6. The system of claim 4, wherein the length for the current time interval is equal to about 10 microseconds.
7. The system of claim 1, wherein the desired memory power consumption rate is equal to about 66 percent of a maximum power consumption of the at least one DRAM module.
8. The system of claim 1, wherein the desired memory power consumption rate is equal to about 9 watts for each of the at least one DRAM module.
9. The system of claim 1, wherein the processor includes the DRAM controller.
10. A method for limiting power consumption of a computer memory system comprising:
selecting a memory access rate, the selected memory access rate corresponds to a desired average memory power consumption rate;
starting a first time interval as a current time interval;
accessing a memory system;
if the memory access rate has not been exceeded, then applying the access to the memory system; and
if the memory access rate has been exceeded, then:
delaying the access until the current time interval has expired;
starting a subsequent time interval as the current time interval; and
applying the access to the memory system.
11. The method of claim 10, wherein accessing the memory system can include:
determining if the current time interval has expired, if the current time interval has expired, then:
starting a subsequent time interval as the current time interval; and
applying the access to the memory system.
12. The method of claim 11, wherein if the current time interval has not expired then incrementing an access counter.
13. The method of claim 10, wherein the access rate is equal to a number of accesses per a current time interval.
14. The method of claim 10, wherein selecting the memory access rate includes selecting a length for the current time interval.
15. The method of claim 14, wherein the length for the current time interval is less than a regulation time constant of a power supply of the computer system.
16. The method of claim 14, wherein the length for the current time interval is equal to about 10 microseconds.
17. The method of claim 10, wherein the desired memory power consumption rate is equal to about 66 percent of a maximum power consumption of each memory module in the memory system.
18. The method of claim 10, wherein the desired memory power consumption rate is equal to about 9 watts per memory module in the memory system.
19. The method of claim 10, wherein a DRAM controller controls access to the memory system.