1. A gain stage control method comprising:
providing a control current signal;
generating a regulation current signal related to the control current signal;
transforming the regulation current signal into a biasing current that is proportional to the regulation current signal and is related to the control current signal by an exponential law of a type
IPOL=K1exp(K2ICTRL)
with:
IPOL being the baising current,
ICTRL being the control current signal, and
K1 and K2 being multiplicative constants; and biasing the gain stage using the biasing current.
2. The control method according to claim 1 wherein the control current signal comprises a PTAT control signal.
3. The control method according to claim 1 further comprising generating the control current signal by converting a control voltage signal according to a linear relation of direct proportionality.
4. The control method according to claim 3 wherein generating the control current signal comprises:
providing a first steady-temperature current signal;
providing a second PTAT current signal; and
generating the control current signal according to a relation:
I
CTRL
=
K
3
\u2062
I
2
I
1
\u2062
V
CTRL
with:
I1 being the first steady-temperature current signal,
I2 being the second PTAT current signal,
VCTRL being the control voltage signal, and
K3 being a multiplicative constant.
5. A method for generating a biasing current for a gain stage comprising:
generating a regulation current signal based upon a control current signal; and
transforming the regulation current signal into a biasing current based upon the regulation current signal and so that the biasing current is related to the control current signal by an exponential law of a type:
IPOL=K1exp(K2ICTRL)
with:
IPOL being the biasing current,
ICTRL being the control current signal, and
K1 and K2 being multiplicative constants.
6. The method according to claim 5 wherein the control current signal comprises a PTAT control current signal.
7. The method according to claim 5 further comprising generating the control current signal by converting a control voltage signal according to a linear relation of direct proportionality.
8. The control method according to claim 7 wherein generating the control current signal comprises:
providing a first steady-temperature current signal;
providing a second PTAT current signal; and
generating the control current signal according to a relation:
I
CTRL
=
K
3
\u2062
I
2
I
1
\u2062
V
CTRL
with:
I1 being the first steady-temperature current signal,
I2 being the second PTAT current signal,
VCTRL being the control voltage signal, and
K3 being a multiplicative constant.
9. An output power control circuit for a gain stage comprising:
a control circuit generating a regulation current signal according to an exponential law with respect to a control voltage signal and comprising
an input transistor having a control terminal,
an output transistor having a control terminal, a first conduction terminal connected to a reference voltage and a second conduction terminal connected to said biasing circuit, and
at least one operational amplifier having a first input terminal connected to the control terminal of said input transistor, a second input terminal to receive the control voltage signal, and an output terminal connected to the control terminal of said output transistor; and
a biasing circuit connected to said control circuit and generating a biasing current for a control terminal of the gain stage according to a linear relation with respect to the regulation current signal.
10. The output power control circuit according to claim 9 wherein said input transistor comprises a first conduction terminal connected to the reference voltage and a second conduction terminal; and further comprising a reference current generator connected to said second conduction terminal of said input transistor.
11. The output power control circuit according to claim 10 wherein said reference current generator is constant with respect to temperature.
12. The output power control circuit according to claim 9 wherein said control circuit comprises a resistor connected between the control terminal of the input transistor and the first input terminal of said operational amplifier.
13. The output power control circuit according to claim 9 wherein said input transistor is diode-configured.
14. The output power control circuit according to claim 9 further comprising a feedback resistor between the output terminal of said operational amplifier and the second input terminal of said operational amplifier.
15. The output power control circuit according to claim 9 further comprising a voltage-current converter having an input terminal receiving the control voltage signal and having an output terminal for a control current signal connected to the second input terminal of the operational amplifier.
16. The output power control circuit according to claim 15 wherein said voltage-current converter comprises a translinear voltage-current converter.
17. The output power control circuit according to claim 15 wherein the control current signal comprises a PTAT control current signal.
18. The output power control circuit according to claim 17 wherein said voltage-current converter generates the control current signal according to the relation:
I
CTRL
=
K
3
\u2062
I
2
I
1
\u2062
V
CTRL
with
ICTRL being the control current signal;
VCTRL being the control voltage signal;
I1 being a steady-temperature current value;
I2 being a PTAT current value; and
K3 being a multiplicative constant.
19. A wireless telecommunications device comprising:
at least one gain stage having a control terminal;
a control circuit generating a regulation current signal according to an exponential law with respect to a control voltage signal and comprising
an input transistor having a control terminal,
an output transistor having a control terminal, a first conduction terminal connected to a reference voltage and a second conduction terminal connected to said biasing circuit, and
at least one operational amplifier having a first input terminal connected to the control terminal of said input transistor, a second input terminal to receive the control voltage signal, and an output terminal connected to the control terminal of said output transistor; and
a biasing circuit connected to said control circuit and generating a biasing current for the control terminal of said at least one gain stage according to a linear relation with respect to the regulation current signal.
20. The wireless telecommunications device according to claim 19 wherein said input transistor comprises a first conduction terminal connected to the reference voltage and a second conduction terminal; and further comprising a reference current generator connected to said second conduction terminal of said input transistor.
21. The wireless telecommunications device according to claim 20 wherein said reference current generator is constant with respect to temperature.
22. The wireless telecommunications device according to claim 19 wherein said control circuit comprises a resistor connected between the control terminal of the input transistor and the first input terminal of said operational amplifier.
23. The wireless telecommunications device according to claim 19 wherein said input transistor is diode-configured.
24. The wireless telecommunications device according to claim 19 further comprising a feedback resistor between the output terminal of said operational amplifier and the second input terminal of said operational amplifier.
25. The wireless telecommunications device according to claim 19 further comprising a voltage-current converter having an input terminal receiving the control voltage signal and having an output terminal for a current control signal connected to the second input terminal of the operational amplifier.
26. The wireless telecommunications device according to claim 25 wherein said voltage-current converter comprises a translinear voltage-current converter.
27. The wireless telecommunications device according to claim 25 wherein the control current signal comprises a PTAT control current signal.
28. The wireless telecommunications device according to claim 27 wherein said voltage-current converter generates the control current signal according to the relation:
I
CTRL
=
K
3
\u2062
I
2
I
1
\u2062
V
CTRL
with
ICTRL being the control current signal;
VCTRL being the control voltage signal
I1 being a steady-temperature current value;
I2 being a PTAT current value; and
K3 being a multiplicative constant.
29. A gain stage control method comprising:
providing a first control current signal;
generating a regulation current signal related to the first control current signal;
transforming the regulation current signal into a biasing current that is proportional to the regulation current signal and is related to the first control current signal by an exponential law;
biasing the gain stage using the biasing current; and
generating the first control current signal by converting a control voltage signal according to a linear relation of direct proportionality by
providing a first steady-temperature current signal,
providing a second PTAT current signal, and
generating the first control current signal according to a relation:
I
CTRL
=
K
3
\u2062
I
2
I
1
\u2062
V
CTRL
with:
ICTRL being the first control current signal,
I1 being the first steady-temperature current signal,
I2 being the second PTAT current signal,
VCTRL being the control voltage signal, and
K3 being a multiplicative constant.
30. A method for generating a biasing current for a gain stage comprising:
generating a regulation current signal based upon a first control current signal;
transforming the regulation current signal into a biasing current based upon the regulation current signal and so that the biasing current is related to the first control current signal by an exponential law; and
generating the first control current signal by converting a control voltage signal according to a linear relation of direct proportionality by
providing a first steady-temperature current signal,
providing a second PTAT current signal, and
generating the first control current signal according to a relation:
I
CTRL
=
K
3
\u2062
I
2
I
1
\u2062
V
CTRL
with:
ICTRL being the first control current signal,
I1 being the first steady-temperature current signal,
I2 being the second PTAT current signal,
VCTRL being the control voltage signal, and
K3 being a multiplicative constant.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Apparatus comprising:
an automated banking machine including:
a cash dispenser;
a check imaging device;
a marking device, wherein the marking device is operative to mark indicia on a check received by the machine;
at least one processor in the machine, wherein the at least one processor is in operative connection with the check imaging device;
wherein the at least one processor is operative to generate marked image data corresponding to a visual image of at least one side of the check marked with indicia through operation of the marking device;
wherein the at least one processor is operative to change the marked image data to produce modified marked image data, wherein at least some data that corresponds to indicia marked on the check through operation of the marking device is not included in the modified marked image data.
2. The apparatus according to claim 1 wherein the automated banking machine further includes:
a communication device, wherein the communication device is operative to send the modified marked image data from the automated banking machine to a remote computer.
3. The apparatus according to claim 1 wherein the automated banking machine further includes:
a communication device, wherein the communication device is in operative connection with the at least one processor, wherein the communication device is operative to send the modified marked image data from the automated banking machine to a remote computer, and wherein the at least one processor is operative to cause the communication device to send first data to the remote computer, wherein the first data corresponds to at least some of the data included in the marked image data which is not included in the modified marked image data.
4. The apparatus according to claim 1 wherein the automated banking machine includes at least one customer input device, wherein the at least one customer input device is operative to receive identifying data corresponding to at least one of a customer and a customer account associated with a transaction in which the check is received in the machine, and wherein the marking device is operative to mark indicia corresponding to at least a portion of the identifying data on the check.
5. The apparatus according to claim 1 wherein the at least one processor is operative to generate at least one authenticity feature, wherein the at least one processor is operative to cause the at least one authenticity feature to be included in at least one of the marked image data and the modified marked image data.
6. The apparatus according to claim 1 wherein the check includes a micr line thereon, and wherein the marked image data includes data corresponding to the micr line, and wherein the at least one processor is further operative to modify data corresponding to at least a portion of the micr line.
7. The apparatus according to claim 1 wherein the at least one processor is operative to cause the automated banking machine to carry out a transaction in which the check is received, and wherein the at least one processor is operative to generate at least one markup language document, wherein the at least one markup language document includes data corresponding to the transaction.
8. The apparatus according to claim 1 wherein the at least one processor is operative to generate image overlay data, wherein the image overlay data corresponds to at least some of the indicia marked on the check through operation of the marking device, wherein the at least one processor is operative to generate at least some of the modified marked image data responsive to the image overlay data.
9. The apparatus according to claim 1 wherein the automated banking machine further includes a clock device, wherein the clock device is operative to determine a current time, and wherein the indicia marked by the marking device on the check includes indicia corresponding to a time associated with receipt of the check by the automated banking machine.
10. The apparatus according to claim 1 wherein the automated banking machine further includes at least one data store, wherein the at least one data store is in operative connection with the at least one processor, wherein the at least one data store includes identifying data corresponding to the automated banking machine, and wherein indicia marked on the check through operation of the marking device corresponds to the identifying data.
11. Apparatus comprising:
a machine including:
a check imaging device;
a marking device, wherein the marking device is operative to mark indicia on a check received by the machine;
at least one processor in the machine, wherein the at least one processor is operative to receive data generated responsive to operation of the check imaging device;
wherein the at least one processor is operative to generate marked image data corresponding to a visual image of at least one side of the check marked with indicia through operation of the marking device;
wherein the at least one processor is operative to change the marked image data to produce modified marked image data, wherein at least some data corresponding to indicia marked on the check through operation of the marking device is not included in the modified marked image data.
12. The apparatus according to claim 11, wherein the machine further comprises a cash dispenser, and wherein the machine comprises an automated banking machine.
13. The apparatus according to claim 11 wherein the machine further includes:
a communication device, wherein the communication device is in operative connection with the at least one processor, wherein the communication device is operative to send the modified marked image data from the machine to a remote computer.
14. The apparatus according to claim 11 wherein the machine includes at least one customer input device, wherein the at least one customer input device is operative to receive identifying data corresponding to at least one of a customer and a customer account associated with a transaction in which a check is received in the machine, wherein the at least one processor is in operative connection with the at least one customer input device, wherein the at least one processor is in operative connection with the marking device, and wherein the at least one processor is operative to cause the marking device to mark indicia corresponding to at least a portion of the identifying data on a received check.
15. The apparatus according to claim 11 wherein the at least one processor is operative to generate at least one authenticity feature, wherein the at least one processor is operative to cause the at least one authenticity feature to be included in at least one of the marked image data and the modified marked image data.
16. The apparatus according to claim 11 wherein the machine is operative to receive a check including a micr line, wherein the at least one processor is operative to generate marked image data that includes micr line data corresponding to a micr line of a received check, and wherein the at least one processor is further operative to modify at least a portion of the micr line data.
17. The apparatus according to claim 11 wherein the at least one processor is operative to cause the machine to carry out a transaction in which a check is received by the machine, and wherein the at least one processor is operative to generate at least one markup language document including data associated with the transaction.
18. The apparatus according to claim 11 wherein the at least one processor is operative to generate image overlay data, wherein the image overlay data corresponds to at least some indicia marked on a received check through operation of the marking device, and wherein the at least one processor is operative to generate at least some modified marked image data responsive to the image overlay data.
19. The apparatus according to claim 11 wherein the machine further includes a clock device, wherein the clock device is operative to determine a current time, wherein the at least one processor is in operative connection with the marking device, and wherein the at least one processor is operative to cause the marking device to mark indicia on a received check that corresponds to a time associated with receipt of the check by the machine.
20. The apparatus according to claim 11 and further comprising at least one data store, wherein the at least one data store includes identifying data corresponding to the machine, wherein the at least one processor is in operative connection with the at least one data store, wherein the at least one processor is in operative connection with the marking device, and wherein the at least one processor is operative to cause the marking device to mark indicia on a received check that corresponds to the identifying data.