1. An integrated circuit comprising:
a plurality of leads, a sequence of black area pixel values being present on the plurality of leads; and
smear detect circuitry that receives the sequence of black area pixel values and outputs a smear detect signal.
2. The integrated circuit of claim 1, wherein the integrated circuit is coupled to an image sensor, the image sensor includes a transfer line and a black area, and the smear detect signal indicatives that a charge has leaked along the transfer line and into the black area.
3. The integrated circuit of claim 1, wherein the integrated circuit is an analog front end (AFE) integrated circuit of a digital camera.
4. The integrated circuit of claim 1, further comprising:
a black level generator that receives the smear detect signal and outputs a black level value.
5. The integrated circuit of claim 4, wherein the black level generator is disabled when the smear detect signal is asserted.
6. The integrated circuit of claim 1, further comprising:
a second plurality of leads that communicates a threshold value to the smear detect circuitry.
7. The integrated circuit of claim 6, wherein the smear detect circuitry comprises:
a comparator that receives the sequence of black area pixel values and the threshold value and outputs a logic signal; and
a state machine that receives the logic signal and outputs the smear detect signal.
8. The integrated circuit of claim 1, wherein the smear detect circuitry detects when a predetermined threshold value is exceeded by more than a predetermined number of consecutive black area pixel values.
9. The integrated circuit of claim 1, wherein the smear detect signal is output from the integrated circuit.
10. The integrated circuit of claim 1, wherein the integrated circuit is an image sensor integrated circuit.
11. The integrated circuit of claim 1, wherein the integrated circuit is part of a digital camera that produces a digital image, wherein the digital image is stored in the digital camera as a digital file, and wherein information from the smear detect signal is included in the digital file.
12. An image sensor integrated circuit that outputs a smear detect signal.
13. The image sensor integrated circuit of claim 12, wherein the image sensor integrated circuit includes an optical black area, and wherein the smear detect signal indicates that smear leakage has leaked into the optical black area.
14. An integrated circuit comprising:
a plurality of leads, a sequence of black area pixel values being present on the plurality of leads; and
means for outputting a smear detect signal in response to detecting smear resulting from a charge leaking along a transfer line of an image sensor and into a black area of the image sensor.
15. A method comprising:
(a) detecting a leakage charge that leaks from a first storage element to a second storage element of an image sensor, wherein the first storage element and the second storage element are located along a transfer line; and
(b) identifying the transfer line as exhibiting the leakage charge.
16. The method of claim 15, wherein the image sensor is a charge coupled device in an analog front end (AFE) of a digital camera.
17. The method of claim 15, wherein the first storage element has been exposed to bright light, and wherein the second storage element is located in an optical black area of the image sensor.
18. The method of claim 15, further comprising:
(c) indicating that the leakage charge has leaked.
19. The method of claim 18, wherein the image sensor is a charge coupled device in a digital camera, wherein the digital camera has a display, and wherein the leakage charge is indicated in (c) by displaying an icon on the display of the digital camera.
20. The method of claim 18, wherein the image sensor is part of a digital camera that produces a digital image, wherein the digital image is stored in the digital camera as a file with a filename, and wherein the leakage charge is indicated in (c) by including a code in the filename of the digital image.
21. The method of claim 15, wherein each storage element stores an amount of charge, wherein pixel data includes the amount of charge stored on each storage element, further comprising:
(c) performing black level calibration of the pixel data, wherein pixel data from the transfer line is excluded from the black level calibration.
22. The method of claim 15, wherein the image sensor includes a second transfer line adjacent to the first-mentioned transfer line, wherein plural storage elements are located along the second transfer line, wherein pixel data includes the amount of charge stored on each of the plural storage elements located along the second transfer line, further comprising:
(c) performing black level calibration of the image sensor, wherein pixel data from the second transfer line is excluded from the black level calibration.
23. The method of claim 15, wherein plural adjacent storage elements are located along the transfer line, wherein each of the plural adjacent storage elements stores an amount of charge, and wherein the leakage charge is detected in (a) when the amount of charge stored on each of N consecutive adjacent storage elements exceeds a threshold amount, wherein N is an integer greater than one.
24. The method of claim 15, wherein the image sensor includes plural transfer lines, and wherein each of the plural transfer lines is located partially within an optical black area.
25. The method of claim 15, wherein the image sensor is part of a digital camera, wherein the digital camera contains a microcontroller, further comprising:
(c) sending an interrupt signal to the microcontroller upon detecting the leakage current in (a).
26. A device comprising:
a first storage element located along a transfer line;
a second storage element located along the transfer line, wherein the first storage element and the second storage element are part of an image sensor; and
smear detect circuitry that detects when a leakage charge leaks from the first storage element to the second storage element.
27. The device of claim 26, wherein the image sensor is a charge coupled device in an analog front end (AFE) of a digital camera.
28. The device of claim 26, wherein plural adjacent storage elements are located along the transfer line, wherein each of the plural adjacent storage elements stores an amount of charge, and wherein the smear detect circuitry detects the leakage charge when the amount of charge stored on each of N consecutive adjacent storage elements exceeds a threshold amount, wherein N is an integer greater than one.
29. The device of claim 26, further comprising:
a black level generator that calculates a black level value of the image sensor.
30. The device of claim 29, wherein the image sensor includes a plurality of storage elements, wherein each storage element stores an amount of charge, wherein the amount of charge stored on each storage element constitutes pixel data, and wherein the black level generator calculates the black level value of the image sensor by excluding pixel data from the transfer line.
31. The device of claim 26, wherein the image sensor includes a plurality of storage elements, wherein each storage element stores an amount of charge, wherein the amount of charge stored on each storage element constitutes pixel data, wherein the black level generator receives pixel data from the image sensor, and wherein the black level generator is disabled when the image sensor outputs pixel data from the transfer line.
32-49. (canceled)
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit layout, said integrated circuit layout comprising:
a plurality of circuit module designs;
a first interconnect line layer, said first interconnect line layer having a preferred horizontal direction of interconnect lines;
a second interconnect line layer, said second interconnect line layer having a preferred vertical direction of interconnect lines; and
a third interconnect line layer, said third interconnect line layer having a first diagonal preferred direction of interconnect lines;
wherein a plurality of interconnect lines on said first second, and third interconnect line layers couple said plurality of circuit module designs, said plurality of interconnect lines generated by using gridless routing, said gridless routing resulting in at least one pair of parallel interconnect lines on one of said interconnect line layers being closer than a minimum required line-to-via spacing.
2. The integrated circuit layout as claimed in claim 1, said integrated circuit layout further comprising:
a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines, said second diagonal preferred direction orthogonal to said first diagonal preferred direction.
3. The integrated circuit layout as claimed in claim 2, wherein said first diagonal preferred direction is approximately forty-five degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately negative forty-five degrees relative to said preferred horizontal direction.
4. The integrated circuit layout as claimed in claim 1, said integrated circuit layout further comprising:
a fourth interconnect line layer, said fourth interconnect line layer having a preferred horizontal direction of interconnect lines.
5. The integrated circuit layout as claimed in claim 4, said integrated circuit layout further comprising:
a fifth interconnect line layer, said fifth interconnect line layer having a second diagonal preferred direction of interconnect lines, said second diagonal preferred direction orthogonal to said first diagonal preferred direction.
6. The integrated circuit layout as claimed in claim 1, said integrated circuit layout further comprising:
a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines;
wherein said first diagonal preferred direction is approximately sixty degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately negative sixty degrees relative to said preferred horizontal direction.
7. The integrated circuit layout as claimed in claim 1, said integrated circuit layout further comprising:
a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines;
wherein said first diagonal preferred direction is approximately negative sixty degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately positive thirty degrees relative to said preferred horizontal direction.
8. The integrated circuit layout as claimed in claim 1, wherein said integrated circuit layout is formed by compacting a gridded integrated circuit layout.
9. The integrated circuit layout as claimed in claim 1, wherein said pair of parallel interconnect lines may be placed as close together as can be manufactured reliably.
10. The integrated circuit layout as claimed in claim 1, wherein vias couple interconnect lines on different interconnect line layers.
11. A method of laying out an integrated circuit, said method comprising:
placing a plurality of circuit module designs;
routing a first interconnect line layer, said first interconnect line layer having a preferred horizontal direction of interconnect lines;
routing a second interconnect line layer, said second interconnect line layer having a preferred vertical direction of interconnect lines; and
routing a third interconnect line layer, said third interconnect line layer having a first diagonal preferred direction of interconnect lines;
wherein a plurality of interconnect lines on said first, second, and third interconnect line layers couple said plurality of circuit module designs, said plurality of interconnect lines generated by using gridless routing, said gridless routing resulting in at least one pair of parallel interconnect lines on one of said interconnect line layers being closer than a minimum required line-to-via spacing.
12. The method of laying out said integrated circuit layout as claimed in claim 11, said method further comprising;
routing a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines, said second diagonal preferred direction orthogonal to said first diagonal preferred direction.
13. The method of laying out said integrated circuit layout as claimed in claim 11, wherein said first diagonal preferred direction is approximately forty-five degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately negative forty-five degrees relative to said preferred horizontal direction.
14. The method of laying out said integrated circuit layout as claimed in claim 11, said method further comprising:
routing a fourth interconnect line layer, said fourth interconnect line layer having a preferred horizontal direction of interconnect lines.
15. The method of laying out said integrated circuit layout as claimed in claim 14, said method further comprising:
routing a fifth interconnect line layer, said fifth interconnect line layer having a second diagonal preferred direction of interconnect lines, said second diagonal preferred direction orthogonal to said first diagonal preferred direction.
16. The method of laying out said integrated circuit layout as claimed in claim 11, said method further comprising:
routing a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines;
wherein said first diagonal preferred direction is approximately sixty degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately negative sixty degrees relative to said preferred horizontal direction.
17. The method of laying out said integrated circuit layout as claimed in claim 11, said method further comprising:
routing a fourth interconnect line layer, said fourth interconnect line layer having a second diagonal preferred direction of interconnect lines;
wherein said first diagonal preferred direction is approximately negative sixty degrees relative to said preferred horizontal direction and said second diagonal preferred direction is approximately positive thirty degrees relative to said preferred horizontal direction.
18. The method of laying out said integrated circuit layout as claimed in claim 11, wherein said integrated circuit layout is formed by compacting a gridded integrated circuit layout.
19. The method of laying out said integrated circuit layout as claimed in claim 11, wherein said pair of parallel interconnect lines may be placed as close together as can be manufactured reliably.
20. The method of laying out said integrated circuit layout as claimed in claim 11, wherein vias couple interconnect lines on different interconnect line layers.
21. An integrated circuit layout, said integrated circuit layout comprising:
a plurality of circuit modules;
a first interconnect line layer, said first interconnect line layer having a first preferred direction of interconnect lines;
a second interconnect line layer, said second interconnect line layer having a second preferred direction of interconnect lines, wherein said first and second preferred directions of interconnect lines are neither orthogonal nor parallel; and
a plurality of interconnect lines on said first and second interconnect line layers;
wherein said plurality of interconnect lines couple said circuit modules;
wherein said plurality of interconnect lines are not aligned with any grid other than a manufacturing grid.
22. The integrated circuit layout of claim 21, wherein said plurality of interconnect lines coupling said circuit modules comprise a route.
23. The integrated circuit layout of claim 21, wherein the angle between said first and second preferred directions is less than ninety degrees.
24. The integrated circuit layout of claim 21, wherein the angle between said first and second preferred directions is forty-five degrees.
25. The integrated circuit layout of claim 21, wherein the angle between said first and second preferred directions is one hundred thirty-five degrees.