What is claimed is:
1. A method of fabricating a semiconductor transistor, comprising:
forming a gate pattern on a semiconductor substrate;
forming a first insulating layer on an entire surface of the substrate including the gate pattern;
forming L-shaped third and second spacers which are sequentially stacked on the first insulating layer on a sidewall of the gate pattern, the third and second spacers each having a horizontal protruding portion;
simultaneously forming high- and medium-concentration junction areas in the substrate beyond the L-shaped second spacer and in the substrate under the horizontal protruding portion of the L-shaped second spacer, respectively, by performing a high-concentration ion implantation process using the L-shaped second spacer and the gate pattern as an ion implantation mask;
annealing the substrate having undergone the high-concentration ion implantation process;
removing the L-shaped second spacer; and
forming a low-concentration junction area under the horizontal protruding portion of the L-shaped third spacer by performing a low-concentration ion implantation process using the L-shaped third spacer and the gate pattern as an ion implantation mask.
2. The method as claimed in claim 1, wherein forming the L-shaped third and second spacers comprises:
forming second, third, and fourth insulating layers which are sequentially stacked on the first insulating layer;
anisotropically etching the fourth insulating layer to form a first spacer on the sidewall of the third insulating layer;
etching the third insulating layer, using the first spacer as an etch mask, to form an L-shaped second spacer having a horizontal protruding portion under the first spacer; and
etching the second insulating layer at the same time as removing the first spacer to form an L-shaped third spacer having a horizontal protruding portion under the L-shaped second spacer.
3. The method as claimed in claim 1, wherein the first insulating layer is made of silicon oxide.
4. The method as claimed in claim 2, wherein the second insulating layer is made of material having an etch selectivity with respect to the first insulating layer.
5. The method as claimed in claim 2, wherein the third insulating layer is made of material having an etch selectivity with respect to the second insulating layer.
6. The method as claimed in claim 2, wherein the fourth insulating layer is made of material having an etch selectivity with respect to the third insulating layer.
7. The method as claimed in claim 2, wherein removing the first spacer uses an isotropic etch technique.
8. The method as claimed in claim 1, wherein removing the L-shaped second spacer uses an isotropic etch technique.
9. The method as claimed in claim 1, wherein removing the L-shaped second spacer includes etching the first insulating layer exposed on the gate pattern and beyond the L-shaped third spacer to expose a top surface of the gate pattern and to form an L-shaped fourth spacer having a horizontal protruding portion under the L-shaped third spacer.
10. The method as claimed in claim 9, further comprising forming a silicide layer on the substrate at both sides of the L-shaped fourth spacer and on the gate pattern, after the low-concentration ion implantation process is performed.
11. The method as claimed in claim 1, wherein the annealing process step is a rapid thermal process (RTP).
12. The method as claimed in claim 1, wherein forming the medium- and high-concentration junction areas causes the medium-concentration junction area to have a lower impurity concentration than the high-concentration junction area, using the protruding portions of the L-shaped second and third spacers and the first insulating layer as an ion channeling barrier layer.
13. A semiconductor transistor comprising:
a gate pattern formed on a semiconductor substrate;
an L-shaped third spacer having a horizontal protruding portion, the third spacer being formed on a sidewall surface of the gate pattern;
an L-shaped fourth spacer having a vertical sidewall between a vertical sidewall of the L-shaped third spacer and the gate pattern and a horizontal protruding portion between the protruding portion of the L-shaped third spacer and the substrate;
a high-concentration junction area formed in the substrate beyond the L-shaped third spacer;
a low-concentration junction area formed in the substrate under the horizontal protruding portion of the L-shaped third spacer; and
a medium-concentration junction area positioned between the high- and low-concentration junction areas.
14. The semiconductor transistor as claimed in claim 13, wherein the medium- and low-concentration junction areas are formed under the protruding portion of the L-shaped third spacer.
15. The semiconductor transistor as claimed in claim 13, wherein the L-shaped fourth spacer is made of silicon oxide.
16. The semiconductor transistor as claimed in claim 13, wherein the L-shaped third spacer is made of material having an etch selectivity with respect to the L-shaped fourth spacer.
17. The method as claimed in claim 9, wherein the L-shaped third spacer is removed before the low-concentration ion-implantation process is performed.
18. The method as claimed in claim 1, wherein a silicon oxide layer is formed on the substrate before the low concentration ion-implantation process.
19. The method as claimed in claim 4, wherein the second insulating layer is made of a material selected from the group consisting of silicon nitride and silicon oxynitride.
20. The method as claimed in claim 4, wherein the third insulating layer is made of silicon oxide.
21. The method as claimed in claim 6, wherein the fourth insulating layer is made of a material selected from the group consisting of silicon nitride and silicon oxynitride.
22. The method as claimed in claim 1, wherein the first insulating layer is formed to a thickness of between about 2 nm-5 nm.
23. The method as claimed in claim 2, wherein the sum of the thickness of the first and second insulating layers is between about 5 nm-20 nm.
24. The method as claimed in claim 2, wherein the third insulating layer is formed to a thickness of between about 20 nm-70 nm.
25. The method as claimed in claim 2, wherein the fourth insulating layer is formed to a thickness of between about 30 nm-90 nm.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An overheat protection circuit comprising:
a temperature detection circuit;
a bias circuit which allows a bias current to flow in the temperature detection circuit; and
a leak current detection circuit which detects a leak current of a transistor allowing the bias current of the bias circuit to flow,
said leak current detection circuit controlling the bias current when the leak current is detected.
2. The overheat protection circuit according to claim 1, wherein the leak current detection circuit includes:
a first transistor having a gate and a source connected to each other and allowing the leak current to flow,
a first current mirror circuit which mirrors the leak current, and
a pull-up circuit connected to an output of the first current mirror circuit.
3. The overheat protection circuit according to claim 1, wherein the bias circuit includes:
a first current source,
a first current mirror circuit which mirrors a current of the first current source and allows the bias current to flow, and
a switch circuit which controls the operation of the first current mirror circuit in response to a signal from the leak current detection circuit.
4. The overheat protection circuit according to claim 3, wherein the bias circuit further includes a second current mirror circuit which mirrors the current of the first current source and allows the bias current to flow.
5. The overheat protection circuit according to claim 2, wherein the bias circuit includes:
a first current source,
a first current mirror circuit which mirrors the current of the first current source and allows the bias current to flow, and
a switch circuit which controls the operation of the first current mirror circuit in response to the signal from the leak current detection circuit.
6. The overheat protection circuit according to claim 5, wherein the bias circuit further includes a second current mirror circuit which mirrors the current of the first current source and allows the bias current to flow.
7. A voltage regulator comprising:
a reference voltage circuit which outputs a reference voltage;
an output transistor which outputs an output voltage from an output terminal;
an error amplifier circuit which amplifies a difference between a divided voltage obtained by dividing the output voltage and the reference voltage and outputs the same therefrom, and controls a gate of the output transistor; and
the overheat protection circuit according to any of claims 1 to 6, which controls the gate of the output transistor.