1. A semiconductor device, comprising:
a substrate;
an ILD (inter layer dielectric) disposed on the substrate;
a TSV (through silicon via) penetrating the substrate and the ILD; and
a contact ring, disposed in the ILD and surrounding the TSV, wherein the contact ring comprises a hollowed center region completely therethrough, the contact ring is an entirely enclosed structure, and parts of the ILD are disposed between the contact ring and the TSV.
2. The semiconductor device of claim 1, further comprising a metal trace disposed on a surface of the ILD, wherein the TSV contacts the metal trace.
3. The semiconductor device of claim 2, wherein the contact ring is electrically connected to the metal trace.
4. The semiconductor device of claim 2, further comprising a barrier layer disposed in the TSV, wherein the barrier layer substantially contacts the metal trace, and the barrier layer is located inside the ILD.
5. The semiconductor device of claim 1, further comprising a liner disposed in the TSV, wherein the liner is only disposed in the substrate.
6. The semiconductor device of claim 1, further comprising a gate structure disposed on the substrate, and the gate structure includes a metal gate, a polysilicon gate or a dummy gate.
7. The semiconductor device of claim 1, further comprising at least a STI (shallow trench isolation) disposed in the substrate, wherein the contact ring is disposed on the STI.
8. A semiconductor device, comprising:
a substrate;
an ILD (inter layer dielectric) disposed on the substrate;
a TSV (through silicon via) penetrating the substrate and the ILD;
a contact ring disposed surrounding the TSV side by side lie within a same plane, the contact ring comprises a hollowed center region completely therethrough, the contact ring is an entirely enclosed structure, and parts of the ILD are disposed between the contact ring and the TSV; and
a liner disposed in the TSV, wherein the liner is only disposed in the substrate.
9. The semiconductor device of claim 8, further comprising a wherein the contact ring disposed in the ILD and surrounding the TSV and a plurality of STI (shallow trench isolation) disposed in the substrate, wherein and the contact ring is disposed on the STI.
10. The semiconductor device of claim 8, further comprising a metal trace disposed on a surface of the ILD, wherein the TSV contacts the metal trace.
11. The semiconductor device of claim 10, wherein the contact ring is electrically connected to the metal trace.
12. The semiconductor device of claim 10, further comprising a barrier layer disposed in the TSV, wherein the barrier layer substantially contacts the metal trace, and the barrier layer is located inside the ILD.
13. The semiconductor device of claim 8, further comprising a gate structure disposed on the substrate, wherein the gate structure includes a metal gate, a polysilicon gate or a dummy gate.
14. The semiconductor device of claim 1, wherein a top surface of the contact ring and the TSV being even with respect to each other.
15. The semiconductor device of claim 8, wherein a top surface of the contact ring and the TSV being even with respect to each other.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A mask-making member comprising:
a plurality of pattern formation regions in which mask circuit patterns are to be formed; and
a supporting region in which any mask circuit pattern is not to be formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other;
wherein said supporting region has first alignment marks used at the time of exposure of a mask made from said mask-making member for forming said mask circuit patterns thereon, and second alignment marks used at the time of exposure of a substrate to be exposed for forming circuit patterns thereon, wherein said first and second alignment marks are formed on a common surface of said supporting region.
2. A mask-making member according to claim 1, wherein said first alignment marks are formed in such a manner that one or more of said first alignment marks are located in a portion, around each of said plurality of pattern formation regions, of said supporting region, and said second alignment marks are formed in such a manner as to be all located in a portion, outside an area formed by said plurality of said pattern formation regions, of said supporting region.
3. A mask-making member according to claim 1, wherein shapes of said first alignment marks are different from those of said second alignment marks.
4. A mask-making member according to claim 1, wherein said mask-making member is a transmission mask-making member.
5. A mask-making member according to claim 1, wherein said mask-making member is a stencil mask-making member.
6. A mask-making member according to claim 4, wherein said first alignment marks and said second alignment marks are formed on an electron scatterer formed on a membrane.
7. A mask-making member according to claim 4, wherein said first alignment marks and said second alignment marks are formed on an electron scatterer formed on a membrane by selectively removing said electron scatterer.
8. A mask-making member according to claim 5, wherein said first alignment marks and said second alignment marks are formed on a mask board.
9. A mask-making member according to claim 5, wherein said first alignment marks and said second alignment marks are formed on a mask board by selectively removing said mask board.
10. A mask-making member according to claim 5, wherein said first alignment marks and said second alignment marks are formed on a mask board by selectively removing said mask board to form holes or grooves in said mask board, and burying said holes or grooves in said mask board, and burying said holes or grooves with a metal whose atoms have atomic weights heavier than those of atoms of said mask board.
11. A mask-making member according to claim 10, wherein said metal is platinum, gold, silver, copper, tungsten, tantalum, or molybdenum.
12. A mask-making member according to claim 1, wherein a stepped position of said first mark is buried with platinum, gold, silver, copper, tungsten, tantalum, or molybdenum.
13. A mask-making member according to claim 1, wherein said second mark is formed outside an area formed by all regions on which mask circuit pattern is to be formed.
14. A mask comprising:
a plurality of pattern formation regions in which mask circuit patterns are formed; and
a supporting region in which any mask circuit pattern is not formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other;
wherein said supporting region has first alignment marks used at the time of exposure of said mask for forming said mask circuit patterns thereon, and second alignment marks used at the time of exposure of a substrate to be exposed for forming circuit patterns thereon.
15. A mask according to claim 14, wherein said first alignment marks are formed in such a manner that one or more of said first alignment marks are located in a portion, around each of said plurality of pattern formation regions, of said supporting region, and said second alignment marks are formed in such a manner as to be all located in a portion, outside an area formed by said plurality of said pattern formation regions, of said supporting region.
16. A mask according to claim 14, wherein shapes of said first alignment marks are different from those of said second alignment marks.
17. A mask according to claim 14, wherein said mask is a transmission mask.
18. A mask according to claim 14, wherein said mask is a stencil mask.
19. A mask according to claim 17, wherein said first alignment marks and said second alignment marks are formed on an electron scatterer formed on a membrane.
20. A mask according to claim 17, wherein said first alignment marks and said second alignment marks are formed on an electron scatterer formed on a membrane by selectively removing said electron scatterer.
21. A mask according to claim 18, wherein said first alignment marks and said second alignment marks are formed on a mask board.
22. A mask according to claim 18, wherein said first alignment marks and said second alignment marks are formed on a mask board by selectively removing said mask board.
23. A mask according to claim 18, wherein said first alignment marks and said second alignment marks are formed on a mask board by selectively removing said mask board to form holes or grooves in said mask board, and burying said holes or grooves with a metal whose atoms have atomic weights heavier than those of atoms of said mask board.
24. A mask according to claim 18, wherein said metal is platinum, gold, silver, copper, tungsten, tantalum, or molybdenum.
25. A mask-making member comprising:
a plurality of pattern formation regions in which mask circuit patterns are to be formed; and
a supporting region in which any mask circuit pattern is not to be formed, said supporting region being provided for holding said plurality of pattern formation regions while separating said plurality of pattern formation regions from each other;
wherein said supporting region has first alignment marks used at the time of exposure of a mask made from said mask-making member for forming said mask circuit patterns thereon, and second alignment marks used at the time of exposure of a substrate to be exposed for forming circuit patterns thereon, wherein said second alignment marks comprises a pattern formed from a plurality of lines with spaces between said lines.