1. A system comprising:
a network comprising a plurality of nodes wherein forwarding is controlled, at least in part, by an optimized spanning tree protocol (OSTP) comprising a selective forwarding state;
a server cluster; and
wherein, in a full-mesh portion of the network, the OSTP
is aware of the full-mesh portion,
is enabled to provide, to the nodes connected by the full-mesh portion, an explicit indication of whether or not full mesh topology is considered established, and
is further enabled to forward packets in one hop between any two of the nodes connected by the full-mesh portion;
wherein the full mesh is a first full mesh;
wherein the server cluster comprises a plurality of servers, each one of a first subset of the servers comprises one or more of the nodes of the network, and a second subset of the first subset of the servers are connected in a second full mesh; and
wherein the second full mesh is identical to the first full mesh.
2. The system of claim 1 wherein a packet sent via any two distinct ones of the nodes of the full-mesh portion from a first one of the nodes outside of the full-mesh to a second one of the nodes outside of the full-mesh portion does not pass through any of the nodes of the full-mesh portion other than the two distinct nodes.
3. The system of claim 1 wherein ports forming connections between the nodes connected by the full-mesh portion use the selective forwarding state.
4. The system of claim 1 wherein the full-mesh portion comprises more than two of the nodes.
5. The system of claim 1 wherein the server cluster is an Enterprise Server (ES) cluster, and the servers are ES-based servers.
6. The system of claim 5 wherein at least some of the second subset of the servers comprise physical partitions of a physically-partitionable symmetric multiprocessor within an ES chassis.
7. The system of claim 1 wherein the second subset of the servers is at least three of the servers.
8. The system of claim 1 wherein each of the second subset of the servers comprises one or more respective ports; and
wherein the full mesh is instantiated among particular ones of the respective ports of the second subset of the servers.
9. The system of claim 8 wherein a type of each of the respective ports is selected from the group consisting of external, internal, regular, and STP edge.
10. The system of claim 8 wherein the particular ports are of the internal type.
11. The system of claim 8 wherein the particular ports exchange messages to, at least in part, establish presence of the full mesh.
12. The system of claim 11 wherein the messages comprise a set of neighbor IDs, each of the neighbor IDs identifying one of the servers.
13. The system of claim 12 wherein the neighbor IDs are MAC addresses.
14. The system of claim 11 wherein the messages are OSTP hello messages.
15. The system of claim 11 wherein the presence of the full mesh is, at least in part, established by a particular one of the second subset of the servers when a plurality of the messages received by the particular server indicate a set of neighbors of the particular server all have each one of the set of neighbors as a neighbor.
16. The system of claim 15 wherein the set of neighbors comprises at least three of the servers.
17. The system of claim 15 wherein subsequent to establishing the presence of the full mesh, each of the particular ports is enabled to use the optimized spanning tree protocol.
18. The system of claim 15 wherein subsequent to establishing the presence of the full mesh, each of the particular ports is enabled to be in the selective forwarding state.
19. The system of claim 18 wherein subsequent to establishing the presence of the full mesh, each of the particular ports is enabled to be in a delay state prior to being enabled to be in the selective forwarding state.
20. The system of claim 15 wherein the messages further comprise a state indicating the establishment of the presence of the full mesh, the state being in accordance with the explicit indication of whether or not full mesh topology is considered established, and subsequent to establishing the presence of the full mesh, a plurality of the messages sent by the particular server have the state indicating the establishment of the presence of the full mesh.
21. The system of claim 20 wherein the full mesh is determined to be valid by the particular server when, subsequent to establishing the presence of the full mesh, a plurality of the messages received by the particular server indicate that each one of the set of neighbors all have the state indicating the establishment of the presence of the full mesh.
22. The system of claim 21 wherein subsequent to determining validity of the full mesh, each of the particular ports is enabled to use the optimized spanning tree protocol.
23. The system of claim 21 wherein subsequent to determining validity of the full mesh, each of the particular ports is enabled to be in the selective forwarding state.
24. The system of claim 23 wherein subsequent to determining validity of the full mesh, each of the particular ports is enabled to be in a delay state prior to being enabled to be in the selective forwarding state.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of operating a flash memory array comprising a plurality of memory blocks, each memory block respectively associated with a counter, the method comprising the steps of:
erasing a selected one of said memory blocks;
responsive to said erasing:
setting the counter associated with said selected one of said memory blocks to a first predetermined value; and
incrementing each counter not associated with said selected one of said memory blocks; and
when a counter equals or exceeds a predetermined threshold value, always refreshing the data in the memory block associated with said counter by:
storing data from the memory block associated with said counter in another one of said memory blocks.
2. A method as in claim 1, wherein said first predetermined value is zero.
3. A method as in claim 1, wherein said refreshing further comprises leaving said data in said different memory block when said refreshing is complete.
4. A method as in claim 1, wherein said refreshing further comprises returning data from said another one of said memory blocks back to the memory block associated with the counter.
5. A method as in claim 4, wherein said data is restored in the same locations in a memory block as it is read from.
6. A method as in claim 1, wherein refreshing comprises dividing said data into pieces, each of said pieces being refreshed after a distinct, unrelated operation is completed by said flash memory array.
7. A method as in claim 6, wherein each of said pieces is refreshed after a write command is executed by said flash memory array.
8. A method as in claim 1, wherein the values of said counters are stored in a table.
9. A method as in claim 8, wherein said table is stored in said flash memory array.
10. A method as in claim 8, wherein said table is stored in a table in a separate memory storage device.
11. A method as in claim 8, wherein the most significant byte and the second most significant byte of each entry in said table are set to predetermined binary values.
12. A method as in claim 11, wherein said predetermined binary values are 11111111 and 11110110.
13. A method as in claim 8, wherein entries in said table contain eight data bytes.
14. A method of operating a flash memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block respectively associated with a counter, the method comprising the steps of:
erasing a memory block;
responsive to said erasing:
setting a counter associated with said memory block to a first predetermined value; and
incrementing counters respectively associated with all other memory blocks in the same main block;
for each counter which equal or exceed a second predetermined value, always refreshing a memory block associated with said counter by storing data contained in said memory block in a different memory block of said flash memory array.
15. A method of operating a flash memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block respectively associated with a counter, the method comprising the steps of:
erasing a memory block;
responsive to said erasing:
setting the counter associated with said memory block to a first predetermined value; and
decrementing the counters associated with all other memory blocks within the same main block;
for each counter which is less than or equal to a second predetermined value, always refreshing a memory block associated with said counter by storing data from said memory block in a different memory block of said flash memory array.
16. A method as in claim 14 or 15, wherein said first predetermined value is zero.
17. A method as in claim 14 or 15, wherein in said step of refreshing, data from blocks being refreshed is restored in the same locations it is read from.
18. A method as in claim 14 or 15, wherein said step of refreshing comprises dividing data in blocks being refreshed into pieces, each of said pieces being refreshed after a distinct, unrelated operation is completed by said flash memory array.
19. A method as in claim 18, wherein each of said pieces is refreshed after a write command is executed by said flash memory array.
20. A method of operating a flash memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block comprising a plurality of sectors each sector respectively associated with a counter, the method comprising the steps of:
programming a sector of one of said memory blocks;
responsive to said programming:
setting a counter associated with the programmed sector to a first predetermined value; and
incrementing each counter associated with each adjacent sector of said one memory block; and
always refreshing the data in a sector of the one memory block of said flash memory array when an associated counter equals or exceeds a predetermined threshold value by storing data contained in that sector to different sector.
21. A method as in claim 20, wherein said first predetermined value is zero.
22. A method as in claim 20, wherein said refreshing further comprises leaving said data in said different sector when said refreshing is complete.
23. A method as in claim 20, wherein said refreshing comprises returning said data from said different sector to said sector.
24. A method as in claim 23, wherein said data is restored in the same locations in a sector as it is read from.
25. A method as in claim 20, wherein when the counters associated with multiple sectors equal or exceed said predetermined threshold simultaneously, said refreshing comprises refreshing some sectors before a distinct, unrelated operation is completed by said flash memory array and refreshing some other sectors after said distinct, unrelated operation is completed by said flash memory array.
26. A method as in claim 25, wherein each of said sectors is refreshed after a next write command is executed by said flash memory array.
27. A method as in claim 20, wherein the values of said counters are stored in a table.
28. A method as in claim 27, wherein said table is stored in said flash memory array.
29. A method as in claim 27, wherein said table is stored in a table in a separate memory storage device.
30. A method as in claim 27, wherein the most significant byte and the second most significant byte of each entry in said table are set to predetermined binary values.
31. A method as in claim 30, wherein said predetermined binary values are 11111111 and 11110110.
32. A method as in claim 27, wherein entries in said table contain eight data bytes.
33. A method of operating a flash memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block comprising a plurality of sectors, each sector respectively associated with a counter, the method comprising the steps of:
programming a sector in a memory block;
responsive to said programming:
setting a counter associated with said sector to a first predetermined value; and
incrementing counters respectively associated with all other sectors adjacent to said programmed sector;
always refreshing all sectors that have associated counters which equal or exceed a second predetermined value by storing data from a sector in a different sector in said flash memory array.
34. A method of operating a flash memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block comprising a plurality of sectors, each sector respectively associated with a counter, the method comprising the steps of:
programming a sector in a memory block;
responsive to said programming:
setting a counter associated with said sector to a first predetermined value;
decrementing counters respectively associated with all other sectors adjacent to said programmed sector; and
always refreshing all sectors that have associated counters which are less than or equal to a second predetermined value by storing data from a sector in a different sector in said flash memory array.
35. A method as in claim 33 or 34, wherein said first predetermined value is zero.
36. A method as in claim 33 or 34, wherein said data is restored in the same locations it is read from.
37. A method as in claim 33 or 34, wherein when the counter associated with multiple sectors equal or exceed said second predetermined value simultaneously, said refreshing comprises refreshing some of said sectors before a distinct, unrelated operation is completed by said flash memory array, and refreshing some other sectors after said distinct, unrelated operation is completed by said flash memory array.
38. A method as in claim 37, wherein each of said pieces is refreshed after a write command is executed by said flash memory array.
39. A flash memory storage device comprising:
a control circuit; and
a data storage area divided into a plurality of memory blocks for storing data and a table for storing a plurality of counters values, each one of said counter values being respectively associated with one of said plurality of memory blocks;
wherein when said control circuit erases data stored in one of said memory blocks, said control circuit sets the counter value associated with said erased memory block to a first predetermined value and increments counter values respectively associated with other memory blocks; and
wherein when one of said plurality of counter values equals or exceeds a predetermined threshold value, said control circuit always refreshes the data in the memory block associated with said counter by storing the data stored in said memory block in a different memory block.
40. A flash memory storage device as in claim 39, wherein said control circuit optimizes said data prior to restoring said data.
41. A flash memory storage device as in claim 39, wherein when a counter value associated with a memory block equals or exceeds said predetermined threshold value, said control circuit divides said data into pieces, said control circuit refreshing some of said pieces before performing a distinct, unrelated operation and some other of said pieces after performing said distinct, unrelated operation.
42. A flash memory storage device as in claim 41, wherein said control circuit refreshes each of said pieces after performing a next write command.
43. A flash memory storage device as in claim 39, wherein the values of said counters are stored in a table.
44. A flash memory storage device as in claim 43, wherein said table is stored in said flash memory storage device.
45. A flash memory storage device as in claim 43, wherein said table is stored in a separate memory storage device.
46. A flash memory storage device as in claim 43, wherein the most significant byte and the second most significant byte of each entry in said table are set to predetermined binary values.
47. A flash memory storage device as in claim 46, wherein said predetermined binary values are 11111111 and 11110110 respectively.
48. A flash memory storage device comprising:
a control circuit; and
a data storage area divided into a plurality of memory blocks, said memory blocks further divided into a plurality of sectors, for storing data and a table for storing a plurality of counter values, each counter value respectively associated with one of said plurality of sectors;
wherein when said control circuit programs one of said sectors, said control circuit sets the counter value associated with said programmed sector to a first predetermined value and increments counter values respectively associated with all sectors adjacent to said programmed sector; and
wherein when one of said plurality of counters equals or exceeds a predetermined threshold value, said control circuit always refreshes the data in the sector associated with said counter by storing the data stored in said sector in a different sector.
49. A flash memory storage device as in claim 48, wherein said control circuit optimizes said data prior to restoring said data.
50. A flash memory storage device as in claim 48, wherein when counters associated with multiple sectors equals or exceed said predetermined threshold value simultaneously, said control circuit refreshes some of said sectors before performing a distinct, unrelated operation and some other of said sectors after performing said distinct, unrelated operation.
51. A flash memory storage device as in claim 50, wherein said control circuit refreshes each of said sectors after performing a next write command.
52. A flash memory storage device as in claim 48, wherein said table is stored in said flash memory storage device.
53. A flash memory storage device as in claim 48, wherein said table is stored in a separate memory storage device.
54. A flash memory storage device as in claim 48, wherein the most significant byte and the second most significant byte of each entry in said table are set to predetermined binary values.
55. A flash memory storage device as in claim 54, wherein said predetermined binary values are 11111111 and 11110110 respectively.
56. A processor circuit comprising:
a processor; and
a flash memory storage device coupled to said processor, said flash memory storage device comprising a plurality of memory storage regions and a plurality of counters, each of said plurality of counters associated with one of said plurality of memory storage regions;
wherein when data stored in one of said memory storage regions is erased, the counter associated with said memory storage region is set to a first predetermined value and the remaining counters are incremented; and
wherein when one of said plurality of counters equals or exceeds a predetermined threshold value, the data in the memory storage region associated with said counter is always refreshed by storing data of said memory storage region in a different memory storage region.
57. A processor circuit as in claim 56, wherein said first predetermined value is zero.
58. A processor circuit as in claim 56, wherein said flash memory storage device restores said data to the same locations.
59. A processor circuit as in claim 56, wherein when a memory storage region requires refreshing, said flash memory storage device divides said memory storage region into pieces, said flash memory storage device refreshing some of said pieces before a distinct, unrelated operation is completed by said flash memory storage device and refreshing some other of said pieces after said distinct, unrelated operation is completed by said flash memory storage device.
60. A processor circuit as in claim 59, wherein said flash memory storage device refreshes each of said pieces after new write commands are executed by said flash memory storage device.
61. A processor circuit as in claim 56, wherein the values of said counters are stored in a table.
62. A processor circuit as in claim 61, wherein said table is stored in said flash memory storage device.
63. A processor circuit as in claim 61, wherein said table is stored in a separate memory storage device.
64. A processor circuit as in claim 61, wherein the most significant byte and the second most significant byte of each table entry are set to a predetermined binary values.
65. A processor circuit as in claim 64, wherein said predetermined binary values are 11111111 and 11110110 respectively.
66. A processor circuit comprising:
a processor; and
a flash memory storage device coupled to said processor, said flash memory storage device comprising a plurality of memory storage regions, said memory storage regions being divided into a plurality of sectors, and a plurality of counters, each of said plurality of counters respectively associated with one of said sectors;
wherein when one of said sectors is programmed, the counter associated with said sector is set to a first predetermined value and all of the sectors adjacent to said programmed sector incremented; and
wherein when one of said plurality of counters equals or exceeds a predetermined threshold value, the data in the sector associated with said counter is always refreshed by storing the data stored in said sector to a different sector.
67. A processor circuit as in claim 66, wherein said first predetermined value is zero.
68. A processor circuit as in claim 66, wherein said flash memory storage device returns said data to said sector.
69. A processor circuit as in claim 66, wherein when the counters associated with multiple sectors equal or exceed said predetermined value simultaneously, said flash memory storage device refreshes some of said sectors before a distinct, unrelated operation is completed by said flash memory storage device, and some other of said sectors after said distinct, unrelated operation is completed by said flash memory storage device.
70. A processor circuit as in claim 69, wherein said flash memory storage device refreshes each of said sectors after a write commands are executed by said flash memory storage device.
71. A processor circuit as in claim 66, wherein the values of said counters are stored in a table.
72. A processor circuit as in claim 71, wherein said table is stored in said flash memory storage device.
73. A processor circuit as in claim 71, wherein said table is stored in a separate memory storage device.
74. A processor circuit as in claim 71, wherein the entries in said table comprise N bytes each, each bit of each entry corresponding to one memory block of N based on said bit’s position within said byte.
75. A processor circuit as in claim 71, wherein the most significant byte and the second most significant byte of each table entry are set to a predetermined binary values, wherein said predetermined binary values are 11111111 and 11110110 respectively.
76. A method of operating a memory array comprising a plurality of memory blocks, each memory block respectively associated with a counter, the method comprising the steps of:
erasing a selected one of said memory blocks;
responsive to said erasing:
setting the counter associated with said selected one of said memory blocks to a first predetermined value; and
incrementing each counter not associated with said selected one of said memory blocks; and
which counter equals or exceeds a predetermined threshold value, always refreshing the data in the memory block associated with said counter by:
storing data from the memory block associated with said counter in another one of said memory blocks.
77. A method of operating a memory array comprising a plurality of main blocks, each main block comprising a plurality of memory blocks, each memory block comprising a plurality of sectors, each sector respectively associated with a counter, the method comprising the steps of:
programming a sector of one of said memory blocks;
responsive to said programming:
setting a counter associated with the programmed sector to a first predetermined value; and
incrementing each counter associated with each adjacent sector of said one memory block; and
always refreshing the data in a sector of the one memory block of said memory array when an associated counter equals or exceeds a predetermined threshold value by storing data contained in that sector to different sector.
78. A memory storage device comprising:
a control circuit; and
a data storage area divided into a plurality of memory blocks for storing data and a table for storing a plurality of counters values, each one of said counter values being respectively associated with one of said plurality of memory blocks;
wherein when said control circuit erases data stored in one of said memory blocks, said control circuit sets the counter value associated with said erased memory block to a first predetermined value and increments counter values respectively associated with other memory blocks; and
wherein when one of said plurality of counter values equals or exceeds a predetermined threshold value, said control circuit always refreshes the data in the memory block associated with said counter by storing the data stored in said memory block in a different memory block.
79. A memory storage device comprising:
a control circuit; and
a data storage area divided into a plurality of memory blocks, said memory blocks further divided into a plurality of sectors, for storing data and a table for storing a plurality of counter values, each counter value respectively associated with one of said plurality of sectors;
wherein when said control circuit programs one of said sectors, said control circuit sets the counter value associated with said programmed sector to a first predetermined value and increments counter values respectively associated with all sectors adjacent to said programmed sector; and
wherein when one of said plurality of counters equals or exceeds a predetermined threshold value, said control circuit always refreshes the data in the sector associated with said counter by storing the data stored in said sector in a different sector.