1. A system for configuring a memory controller that communicates with a memory device, the memory controller including a set of pins, each pin of the set of pins being associated with at least one of a data bit and an address bit, the system comprising:
a programmable logic block connected to the set of pins of the memory controller, the programmable logic block using a subset of the set of pins to enable data transfer between the memory device and the memory controller in accordance with the size of the memory device, wherein the pins outside the subset are available for one or more other applications.
2. The system of claim 1, further comprising a latch connected between the programmable logic block and the memory device, the latch latching multiplexed address and data bits on a plurality of pins of the subset of pins to transfer address and data bits between the memory device and the memory controller.
3. The system of claim 1, wherein the programmable logic block comprises an address shifting block for re-organizing one or more address bits among the set of pins of the memory controller by at least one of:
left shifting the one or more address bits in accordance with the size of the memory device; and
right shifting the one or more address bits in accordance with the size of the memory device.
4. The system of claim 1, wherein the one or more other applications comprises communicating with another memory device.
5. The system of claim 1, wherein the one or more other applications comprises communicating with an inputoutput device.
6. A system for configuring a memory controller, the memory controller suitable for communicating with a memory device, the memory controller including a set of pins, each pin of the set of pins being associated with at least one of a data bit and an address bit, the system comprising:
a programmable logic block connected to the set of pins of the memory controller, the programmable logic block selecting a subset of the set of pins to enable data transfer between the memory device and the memory controller, wherein the selection of the subset is performed by re-organizing one or more address bits among the set of pins of the memory controller in accordance with the size of the memory device;
a multiplexer connected to the programmable logic block for multiplexing address and data bits; and
a latch connected between the multiplexer and the memory device, the latch latching the multiplexed address and data bits on a plurality of pins from the subset of pins to transfer address and data bits between the memory device and the memory controller.
7. The system of claim 6, wherein each of the latch and the multiplexer includes a control pin for receiving a control signal indicating multiplexing of address and data bits, wherein the control signal indicates a transfer of one of the address bits and the data bits.
8. The system of claim 7, wherein multiplexing address and data bits on a plurality of pins comprises multiplexing one or more most significant bits (MSBs) of the address bits with data bits.
9. The system of claim 7, wherein multiplexing address and data bits on a plurality of pins comprises multiplexing one or more least significant bits (LSBs) of the address bits with the data bits.
10. The system of claim 6, wherein the programmable logic block comprises an address shifting block for re-organizing one or more address bits among the set of pins of the memory controller by left shifting the one or more address bits in accordance with the size of the memory device.
11. The system of claim 6, wherein the programmable logic block comprises an address shifting block for re-organizing one or more of the address bits among the set of pins of the memory controller by right shifting the one or more of the address bits in accordance with the size of the memory device.
12. The system of claim 6, wherein the programmable logic block comprises a selector for selecting a second subset of pins for communicating with one or more other applications, the communication being performed using remaining ones of the re-organized address bits, wherein the remaining ones of the re-organized address bits correspond to the second subset of pins.
13. A method for configuring a memory controller that communicates with a memory device, the memory controller including a set of pins, each pin of the set of pins being associated with at least one of a data bit and an address bit, the method comprising:
selecting a subset of the set of pins to enable data transfer between the memory device and the memory controller, the selection of the subset being performed by re-organizing address bits among the set of pins of the memory controller in accordance with the size of the memory device; and
multiplexing address bits and data bits on a plurality of pins of the subset of pins to transfer data between the memory device and the memory controller.
14. The method of claim 13, wherein multiplexing of address and data bits is controlled with a control signal that indicates the transfer of one of the address bits and the data bits.
15. The method of claim 13, wherein multiplexing the address and data bits on a plurality of pins comprises multiplexing one or more most significant bits (MSBs) of the address bits with data bits.
16. The method of claim 13, wherein multiplexing the address and data bits on a plurality of pins comprises multiplexing one or more least significant bits (LSBs) of the address bits with the data bits.
17. The method of claim 13, wherein re-organizing address bits among the set of pins of the memory controller comprises left shifting one or more of the address bits in accordance with the size of the memory device.
18. The method of claim 13, wherein re-organizing address bits among the set of pins of the memory controller comprises right shifting one or more of the address bits in accordance with the size of the memory device.
19. The method of claim 13, wherein the data transfer between the memory device and the memory controller comprises reading data from the memory device.
20. The method of claim 13, wherein the data transfer between the memory device and the memory controller comprises writing data from the memory controller to the memory device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A bonded membrane-electrode assembly system having water-electrolyzing and power-generating functions, comprising a solid polymer electrolyte membrane, an oxygen electrode bonded to one of sides of said solid polymer electrolyte membrane, and a hydrogen electrode bonded to the other side of said solid polymer electrolyte membrane, wherein
said oxygen electrode includes a porous sheet-shaped carbon element plated with iridium, a first coated layer formed on a surface of said sheet-shaped carbon element, which is in contact with said solid polymer electrolyte membrane, by applying a mixture containing carbon and a resin for the solid polymer electrolyte membrane on that surface, and a second coated layer formed on said first coated layer adjacent said solid polymer electrolyte membrane by applying a mixture containing Pt (alloy) andor Pt (alloy)-carried carbon and a resin for the solid polymer membrane electrolyte thereon, and
said hydrogen electrode includes a porous sheet-shaped carbon element, a first coated layer formed on a surface of said sheet-shaped carbon element, which is in contact with said solid polymer electrolyte membrane, by applying a mixture containing carbon and a resin for the solid polymer electrolyte membrane on the surface thereof, and a second coated layer formed on said first coated layer adjacent said solid polymer electrolyte membrane by applying a mixture containing Pt (alloy) andor Pt (alloy)-carried carbon and a resin for the solid polymer electrolyte membrane thereon.
2. A fuel cell provided with a water electrolyzer, comprising a bonded membrane-electrode assembly which comprises at least a pair of bonded membrane-electrode assemblies having water-electrolyzing and power-generating functions and each comprising a solid polymer electrolyte membrane, an oxygen electrode bonded to one of sides of said solid polymer electrolyte membrane, and a hydrogen electrode bonded to the other side of said solid polymer electrolyte membrane; an end plate interposed between the pair of bonded membrane-electrode assemblies; opposite outer end plates between which at least the pair of bonded membrane-electrode assemblies are positioned; a hydrogen flow passage formed through central portions of said bonded membrane-electrode assemblies to permit the flowing of a fluid therethrough; a single tie bolt passed through said hydrogen flow passage in the central portions of said bonded membrane-electrode assemblies to integrate said members; and a fixing nut threadedly fitted over said tie bolt to integrally tighten said bonded membrane-electrode assemblies between said end plates through O-rings or the like threadedly fitted over opposite ends of said tie bolt, wherein
each of said bonded membrane-electrode assemblies includes a flow passage plate adjacent said oxygen electrode, and a separator plate serving as a collector plate and mounted adjacently outside the flow passage plate and outside the hydrogen electrode; one of said bonded membrane-electrode assemblies being immersed in water, and a DC power source being connected to the separator plate of said one bonded membrane-electrode assembly.
3. A fuel cell provided with a water electrolyzer according to claim 2, wherein one of the bonded membrane-electrode assemblies having the water-electrolyzing function comprises
said oxygen electrode including a porous sheet-shaped carbon element plated with iridium, and a coated layer formed on a surface of said sheet-shaped carbon element, which is in contact with said solid polymer electrolyte membrane, by applying a mixture containing carbon and a resin for the solid polymer electrolyte membrane, and
said hydrogen electrode including a porous sheet-shaped carbon element, a first coated layer formed on a surface of said sheet-shaped coated layer element, which is in contact with said solid polymer electrolyte membrane, by applying a mixture containing carbon and a resin for the solid polymer electrolyte membrane on that surface, and a second coated layer formed on said first coated layer adjacent said solid polymer electrolyte membrane by applying a mixture containing Pt (alloy) andor Pt(alloy)-carried carbon and a resin for the solid polymer electrolyte membrane thereon; and
the other of the bonded membrane-electrode assemblies having the power-generating function comprises
each of said oxygen electrode and the hydrogen electrode including a porous sheet-shaped carbon element, a first coated layer formed on a surface of said sheet-shaped carbon element, which is in contact with said solid polymer electrolyte membrane, by applying a mixture containing carbon and a resin for the solid polymer electrolyte membrane on the surface thereof, and a second coated layer formed on said first coated layer adjacent said solid polymer electrolyte membrane by applying a mixture containing Pt (alloy) andor Pt(alloy)-carried carbon and a resin for the solid polymer electrolyte membrane thereon.
4. A fuel cell provided with a water electrolyzer according to claim 2, wherein at least one of the bonded membrane-electrode assemblies comprises
said oxygen electrode including a porous sheet-shaped carbon element plated with iridium, a first coated layer formed on a surface of said sheet-shaped coated layer element, which is in contact with said solid polymer electrolyte membrane, by applying a mixture containing carbon and a resin for the solid polymer electrolyte membrane on that surface, and a second coated layer formed on said first coated layer adjacent said solid polymer electrolyte membrane by applying a mixture containing Pt (alloy) andor Pt(alloy)-carried carbon and a resin for the solid polymer electrolyte membrane thereon, and
said hydrogen electrode including a porous sheet-shaped carbon element, a first coated layer formed on a surface of said sheet-shaped coated layer element, which is in contact with said solid polymer electrolyte membrane, by applying a mixture containing carbon and a resin for the solid polymer electrolyte membrane on the surface thereof, and a second coated layer formed on said first coated layer adjacent said solid polymer electrolyte membrane by applying a mixture containing Pt (alloy) andor Pt(alloy)-carried carbon and a resin for the solid polymer electrolyte membrane thereon.