1. A semiconductor memory comprising:
a plurality of memory cell units, each of the memory cell units including a plurality of memory cells to which a current path is connected in series and to which i-value (i is an integer of 2 or more) data is writable;
a plurality of word lines, each of the word lines being connected to gates of the memory cells arranged in a row direction among the memory cells;
a source line connected to one end of the memory cell units;
a plurality of bit lines each connected to the other end of the memory cell units; and
a control circuit which controls an operation of the memory cell units,
wherein during writing to selected cells connected to a selected word line which is selected as a write target of first k-level data (k is an integer of 2 or more) among the word lines,
in at least one unselected adjacent word line adjacent to the selected word line, the control circuit applies an unselect voltage corrected in accordance with result of reading of data from unselected cells connected to the adjacent word line to the adjacent word line and applies a read voltage to the selected word line to read first (k\u22121)-level data from the selected cells, and
the control circuit writes data to the selected cells in accordance with the read first (k\u22121)-level data and the first k-level data to be written.
2. The semiconductor memory according to claim 1, wherein
the adjacent word line is adjacent to the selected word line on the source line side.
3. The semiconductor memory according to claim 2, wherein
first to j-th thresholds associated with the i-value are set for the respective memory cells, and
when j is indicated by an integer of 4 or more and of i or less, the unselect voltage corrected in accordance with result of data from unselected cells includes a first correction value for (j\u22123)-th and (j\u22121)-th thresholds that are not adjacent to each other, and a second correction value for (j\u22122)-th and j-th thresholds that are not adjacent to each other.
4. The semiconductor memory according to claim 1, wherein
the adjacent word line is adjacent to the selected word line on the bit line side.
5. The semiconductor memory according to claim 1, wherein
in writing the first k-level data to the selected cells,
the unselected cells connected to the adjacent word line adjacent to the selected word line on the source line side store second (k\u22121)-level data and second k-level data, and
the unselected cells connected to the adjacent word line adjacent to the selected word line on the bit line side store third (k\u22121)-level data.
6. The semiconductor memory according to claim 1, wherein
the first (k\u22121)-level data is read from the selected cells before a write voltage to write the first k-level data to the selected cells is applied to the selected word line.
7. A semiconductor memory comprising:
a plurality of memory cell units, each of the memory cell units including a plurality of memory cells to which a current path is connected in series and to which i-value (i is an integer of 2 or more) data is writable;
a plurality of word lines, each of the word lines being connected to gates of memory cells arranged in a row direction among the memory cells;
a source line connected to one end of the memory cell units;
a plurality of bit lines each connected to the other end of the memory cell units; and
a control circuit which controls an operation of the memory cell units,
wherein during writing to selected cells connected to a selected word line which is selected as a write target of first k-level data (k is an integer of 2 or more) among the word lines, before application of a write voltage to write first k-level data to the selected word line,
the control circuit applies a first unselect voltage corrected in accordance with result of reading of data from first unselected cells connected to a first adjacent word line adjacent to the selected word line on the source line side to the first adjacent word line and applies a read voltage to the selected word line to read first (k\u22121)-level data from the selected cells, and
the control circuit applies the write voltage to the selected word line, and writes data to the selected cells in accordance with the read first (k\u22121)-level data and the first k-level data to be written.
8. The semiconductor memory according to claim 7, wherein
first to j-th thresholds associated with the i-value are set for the respective memory cells, and
when j is indicated by an integer of 4 or more and of i or less, the first unselect voltage corrected in accordance with result of reading of data from the first unselected cells includes a first correction value set for (j\u22123)-th and (j\u22121)-th thresholds that are not adjacent to each other, and a second correction value set for (j\u22122)-th and j-th thresholds that are not adjacent to each other.
9. The semiconductor memory according to claim 8, wherein
the first unselect voltage has a pulse shape in which the first correction value and the second correction value succeed, and
the read voltage has a pulse shape constant in voltage value while the first unselect voltage is being applied to the first adjacent word line.
10. The semiconductor memory according to claim 7, wherein
during the writing of the first k-level data to the selected cells,
the first unselected cells connected to the first adjacent word line store second (k\u22121)-level data and second k-level data.
11. The semiconductor memory according to claim 7, wherein
in an unselected second adjacent word line adjacent to the selected word line on the bit line side,
the control circuit applies a second unselect voltage corrected in accordance with result of reading of data from second unselected cells connected to the second adjacent word line to the second adjacent word line while the read voltage is being applied to the selected word line.
12. The semiconductor memory according to claim 11, wherein
the second unselected cells connected to the second adjacent word line store third (k\u22121)-level data.
13. The semiconductor memory according to claim 11, wherein
a pulse shape of the second unselect voltage is different from a pulse shape of the first unselect voltage.
14. The semiconductor memory according to claim 11, wherein
the number of voltage values included in the second unselect voltage is smaller than the number of the voltage values included in the first unselect voltage.
15. The semiconductor memory according to claim 11, wherein
the number of voltage values included in the second unselect voltage is equal to the number of the voltage values included in the first unselect voltage.
16. The semiconductor memory according to claim 7, wherein
the control circuit applies a third unselect voltage having a constant voltage value to unselected word lines other than the first adjacent word line while the first unselect voltage is being applied to the first adjacent word line.
17. A semiconductor memory control method comprising:
writing first (k\u22121)-level (k is an integer of 2 or more) data to a first memory cell selected among a plurality of memory cells in at least one memory cell unit, one end of the memory cell unit being connected to a source line, the other end of the memory cell unit being connected to a bit line, the first memory cell having a gate connected to a first word line, the first word line being adjacent to a second word line on the source line side;
writing second (k\u22121)-level data to a second memory cell in the at least one memory cell unit, the second memory cell having a gate connected to the second word line;
writing first k-level data to the first memory cell;
reading the first (k\u22121)-level data and the first k-level data in the first memory cell;
applying a first unselect voltage corrected in accordance with result of the data reading in the first memory cell to the first word line and applying a read voltage to the second word line to read the second (k\u22121)-level data from the second memory cell; and
writing data to the second memory cell in accordance with the read second (k\u22121)-level data and second k-level data to be written.
18. The semiconductor memory control method according to claim 17, wherein
first to j-th thresholds associated with i-value (i is an integer of 2 or more) data are set for the first and second memory cells, and
when j is indicated by an integer of 4 or more and of i or less, the first unselect voltage includes a first correction value for (j\u22123)-th and (j\u22121)-th thresholds that are not adjacent to each other and a second correction value for (j\u22122)-th and j-th thresholds that are not adjacent to each other, in accordance with result of the data reading in the first memory cell.
19. The semiconductor memory control method according to claim 17, wherein
after the second (k\u22121)-level data is written to the second memory cell, third (k\u22121)-level data is written to a third memory cell in the at least one memory cell unit before reading the second (k\u22121)-level data in the second memory cell, the third memory cell having a gate connected to a third word line, the third word line being adjacent to the second word line on the bit line side,
the third (k\u22121)-level data in the third memory cell is read before reading the second (k\u22121)-level data in the second memory cell, and
a second unselect voltage corrected in accordance with result of the reading of the third (k\u22121)-level data in the third memory cell is applied to the third word line during the reading of the second (k\u22121)-level data in the second memory cell.
20. The semiconductor memory control method according to claim 19, wherein
a pulse shape of the second unselect voltage is different from a pulse shape of the first unselect voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An image pickup apparatus comprising:
image taking mode selecting means for selecting image taking mode information containing information on particular colors determined according to predetermined image taking conditions;
particular color signal extracting means for extracting a video signal of the particular color from an input video signal based on the image taking mode information selected by the image taking mode selecting means;
white balance control amount calculating means for calculating a control amount for controlling the white balance of the input video signal based on the video signal of the particular color extracted by the particular color signal extracting means;
white balance correcting means for correcting the white balance of the input video signal according to the control amount calculated by the white balance control amount calculating means;
color correcting means for correcting the particular color of the video signal corrected by the white balance correcting means into a predetermined color based on a color correction parameter value set for correcting the video signal of the particular color; and
low chroma color suppression processing means for correcting a gain amount of a video signal corresponding to a predetermined area centered at the origin in a color difference plane in the video signal corrected by the color correcting means.
2. The image pickup apparatus as cited in claim 1, wherein;
when said color correcting means corrects the particular color of the video signal into the predetermined color, said color correcting means corrects the particular color into a color corresponding to the position of an intersection of the outmost periphery of the area indicating the predetermined color and a straight line which is connecting a position indicating a corresponding particular color and a central position in an area indicating the predetermined color in the color difference plane.
3. The image pickup apparatus as cited in claim 1, wherein;
said color correcting means is provided with a function for changing the color correction parameter value.
4. The image pickup apparatus as cited in claim 1; wherein;
said image taking mode selecting means is provided with a function which automatically selects the image taking mode information according to image taking environments.
5. An image pickup apparatus comprising:
image taking mode selecting means for selecting desired image taking mode information containing information on particular colors determined according to predetermined image taking conditions;
particular color signal extracting means for extracting a video signal of the particular color from an input video signal based on the image taking mode information selected by the image taking mode selecting means;
white balance control amount calculating means for calculating a control amount for controlling the white balance of the input video signal based on the video signal of the particular color extracted by the particular color signal extracting means;
white balance correcting means for correcting the white balance of the input video signal according to the control amount calculated by the white balance control amount calculating means;
color correcting means for correcting the particular color of the video signal corrected by the white balance correcting means into a predetermined color based on a color correction parameter value which is set for correcting the video signal of the particular color;
low chroma color suppression processing means for correcting a gain amount of a video signal corresponding to a predetermined area centered at the origin in a color difference plane, in the video signal corrected by the color correcting means; and
luminance correcting means for correcting a luminance level of the video signal based on the image taking mode information selected by the image taking mode selecting means.
6. The image pickup apparatus as cited in claim 5, wherein
said luminance correcting means is provided with a function for calculating the proportion of the video signal of the particular color in the video signal and for correcting the luminance level of the video signal of the particular color according to the calculated proportion.
7. The image pickup apparatus as cited in claim 5, wherein;
when said color correcting means corrects the particular color of the video signal into the predetermined color, said color correcting means corrects the particular color into a color corresponding to the position of an intersection of the outmost periphery of the area indicating the predetermined color and a straight line which is connecting a position indicating a corresponding particular color and a central position in an area indicating the predetermined color in the color difference plane.
8. The image pickup apparatus as cited in claim 5, wherein;
said color correcting means is provided with a function for changing the color correction parameter value.
9. The image pickup apparatus as cited in claim 5, wherein;
said image taking mode selecting means is provided with a function for automatically selecting the image taking mode information according to image taking environments.