1. A memory module assembly, comprising:
a plurality of memory modules each equipped with a substrate and memory elements disposed on both of main surfaces of the substrate, wherein said memory modules are arranged in parallel so that said memory modules be installed on a mother board by mounting peripheral sides of said substrates to corresponding connectors provided on the mother board;
plural pairs of heat radiation plates provided correspondingly to said plurality of memory modules so that each memory module is put between the corresponding pair of the heat radiation plates and said memory elements are thermally coupled to the corresponding heat radiation plate, respectively, wherein said plural pairs are arranged spacedly from each other so that the heat radiates from the faces of the heat radiation plates to the air between the neighboring memory modules;
a connecting member disposal at, and thermally coupled to, said heat radiation plates at the peripheral side opposite to said peripheral side to be inserted to the corresponding connector so that the heat generated at the memory elements is conducted from the heat radiation plates, with which the memory elements are thermally coupled, to the other heat radiation plates via said connecting member; and
fixing means arranged to fix the corresponding pair of heat radiation plates by being inserted there through so that said radiation plates closely adhere to the corresponding memory elements.
2. A memory module assembly of claim 1,
wherein each of said heat radiation plates includes a protruding portion which protrudes beyond an extent of the substrate of the corresponding memory module at the peripheral side opposite to said peripheral side to be inserted to the corresponding connector,
wherein said connecting member is disposed at, and thermally coupled to, said heat radiation plates at said protruding portions.
3. A memory module assembly of claim 1, wherein the connecting member is exposed to the air at the surface opposite to the surface facing to the memory modules.
4. A memory module assembly of claim 1, further comprising force-applying means engaged to the corresponding heat radiation plates so that each pair of said radiation plates closely adhere to the memory elements.
5. A memory module assembly of claim 1, further comprising a pair of inner heat radiation plates installed on each of the memory modules so that each inner heat radiation plate is positioned between, and thermally coupled to, a corresponding memory element and a corresponding heat radiation plate.
6. A memory module assembly of claim 1, wherein said heat radiation plates as well as said connecting member are formed of the same material.
7. A memory module assembly of claim 1, wherein said connecting member is provided with plural slits so that the air flows between the heat radiation plates.
8. A memory module assembly of claim 1, wherein the connecting member includes copper.
9. A memory module assembly of claim 4, wherein said force applying means includes a spring.
10. A memory module assembly, comprising:
a plurality of memory modules each equipped with a substrate and memory elements disposed on both of main surfaces of the substrate;
plural pairs of heat radiation plates provided correspondingly to said plurality of memory modules, each memory module being put between the corresponding pair of the heat radiation plates and said memory elements being thermally coupled to the corresponding heat radiation plate, respectively;
a connecting member coupled to pairs of heat radiation plates of the neighboring memory modules installed on a mother board to be inserted to corresponding connectors; and
fixing means arranged to fix the corresponding pair of heat radiation plates by being inserted there through so that radiation plates closely adhere to the corresponding memory elements.
11. A memory module assembly of claim 10, wherein each of said heat radiation plates includes a protruding portion which protrudes beyond an extent of the substrate of the corresponding memory module at the peripheral side opposite to said peripheral side to be inserted to the corresponding connector,
wherein said connecting member is disposed at, and thermally coupled to, said heat radiation plates at said protruding portions.
12. A memory module assembly of claim 10, wherein the connecting member is exposed to the air at the surface opposite to the surface facing to the memory modules.
13. A memory module assembly of claim 1, further comprising force-applying means engaged to the corresponding heat radiation plates so that each pair of said radiation plates closely adhere to the memory elements.
14. A memory module assembly of claim 10, further comprising a pair of inner heat radiation plates installed on each of the memory modules so that each inner heat radiation plate is positioned between, and thermally coupled to, a corresponding memory element and a corresponding heat radiation plate.
15. A memory module assembly of claim 1, wherein said heat radiation plates as well as said connecting member are formed of the same material.
16. A memory module assembly of claim 1, wherein said connecting member is provided with plural slits so that the air flows between the heat radiation plates.
17. A memory module assembly of claim 1, wherein the connecting member includes copper.
18. A memory module assembly of claim 13, wherein said force-applying means includes a spring.
19. A memory module assembly, comprising:
a plurality of memory modules each equipped with a substrate and memory elements disposed on both of main surfaces of the substrate;
plural pairs of heat radiation plates provided correspondingly to said plurality of memory modules, the memory module being put between the corresponding pair of the heat radiation plates and said memory elements being thermally coupled to the corresponding heat radiation plate, respectively,
a connecting member coupled to at least two pairs of heat radiation plates of the neighboring memory modules installed on a mother board to be inserted to corresponding connectors; and
fixing means arranged to fix the corresponding pair of heat radiation plates by being inserted there through so that radiation plates closely adhere to the corresponding memory elements.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for clock synchronization, comprising:
computing an offset value between a local clock time of a real-time clock circuit and a reference clock time;
loading the offset value into a register that is associated with the real-time clock circuit; and
summing the local clock time with the value in the register so as to give an adjusted value of the local clock time that is synchronized with the reference clock.
2. The method according to claim 1, wherein the local clock time is associated with a slave device and the reference clock time is provided by a master device coupled to the slave device via a network.
3. The method according to claim 2, wherein the slave device comprises:
a host processor which is configured to compute the offset value and load the offset value into the register; and
a network interface device comprising the real-time clock circuit.
4. The method according to claim 2, wherein computing the offset value comprises:
exchanging a first set of messages between the master device and the slave device to determine a first time difference comprising the offset value and a transmission delay;
exchanging a second set of messages between the master device and the slave device to determine a second time difference comprising the transmission delay; and
calculating the offset value based on the first and second time differences.
5. The method according to claim 1, wherein the local clock time is maintained by incrementing a counter at intervals determined by a clock source, and wherein summing the local clock time comprises adding the value in the register to the local clock time at one of the intervals.
6. The method according to claim 5, wherein the real-time clock circuit comprises an adder providing a summed output to the counter, and having a first adder input coupled to receive a clock output from the counter, and a second adder input coupled to a multiplexed output from a multiplexer, which has a first multiplexer input coupled to receive a default increment amount and a second multiplexer input coupled to receive the offset value from the register.
7. A real-time clock circuit, comprising:
a counter, which is configured to output a local clock time;
a register, which is coupled to receive an offset value computed by a host processor; and
an adder, which is configured to provide a new local clock time for input to the counter by periodically adding a fixed increment to the local clock time that is output by the counter and alternatively, after the host processor has written the offset value to the register, by summing the offset value from the register with the local clock time.
8. The real-time clock circuit according to claim 7, and comprising a multiplexer having a first multiplexer input coupled to receive a default increment amount and a second multiplexer input coupled to receive the offset value from the register and configured to provide a multiplexed output, wherein the adder has a first input coupled to receive the local clock time that is output by the counter and a second input coupled to the multiplexed output from the multiplexer.
9. The real-time clock circuit according to claim 7, and comprising a local oscillator coupled to output pulses to the counter so as to cause the counter to be incremented at intervals indicated by the pulses.
10. The real-time clock circuit according to claim 7, and comprising a further register, which is coupled to receive an initial time value from a host processor, and a multiplexer, having a first multiplexer input coupled to receive the initial time value from the register, and a second multiplexer input coupled to receive the new local clock time from the adder, and configured to provide a multiplexed output to the counter.
11. An apparatus comprising:
a real-time clock circuit, which is configured to output a local clock time, and which comprises a register, which is coupled to receive an offset value, and an adder, which is coupled to sum the local clock time with the offset value in the register so as to give an adjusted value of the local clock time; and
a host processor configured to compute the offset value between the local clock time and a reference clock time, and to load the offset value into the register.
12. The apparatus according to claim 11, wherein the apparatus comprises a slave device, comprising the real-time clock circuit and the host processor, and the reference clock time is provided by a master device coupled to the slave device via a network.
13. The apparatus according to claim 12, wherein the slave device comprises a network interface device comprising the real-time clock circuit.
14. The apparatus according to claim 12, wherein the host processor is configured to exchange a first set of messages with the master device to determine a first time difference comprising the offset value and a transmission delay, to exchange a second set of messages with the master device to determine a second time difference comprising the transmission delay, and to calculate the offset value based on the first and second time differences.
15. The apparatus according to claim 11, wherein the real-time clock circuit comprises a counter and a clock source and is configured to maintain the local clock time by incrementing the counter at intervals determined by the clock source, and alternatively adding the value in the register to the local clock time at one of the intervals.