1. A Node B comprising:
circuitry configured to receive a first Iub signal from a radio network controller (RNC) indicating a maximum transmit power level for all channel codes transmitted by the Node B; wherein the circuitry is further configured to receive a second Iub signal from the RNC indicating a maximum transmit power level for high speed downlink shared channel (HS-DSCH) and high speed shared control channel (HS-SCCH) codes of the Node B; wherein the circuitry is further configured to transmit at least the HS-DSCH and HS-SCCH codes at a power level that does not exceed the maximum transmit power level for HS-DSCH and HS-SCCH codes of the Node B; and wherein the circuitry is further configured to transmit an Iub signal to the RNC indicating a power associated with the HS-DSCH.
2. The Node B of claim 1 wherein the circuitry is further configured to schedule HS-DSCH transmissions to wireless transmitreceive units (WTRUs).
3. A radio network controller (RNC) comprising:
circuitry configured to transmit a first Iub signal to a Node B indicating a maximum transmit power level for all channel codes transmitted by the Node B; wherein the circuitry is further configured to transmit a second Iub signal to the Node B indicating a maximum transmit power level for high speed downlink shared channel (HS-DSCH) and high speed shared control channel (HS-SCCH) codes of the Node B; and the circuitry is further configured to receive an Iub signal from the Node B indicating a power associated with the HS-DSCH.
4. A method, performed by a Node B, of providing high speed downlink packet access (HSDPA) services, the method comprising:
receiving a first Iub signal from a radio network controller (RNC) indicating a maximum transmit power level for all channel codes transmitted by the Node B;
receiving a second Iub signal from the RNC indicating a maximum transmit power level for high speed downlink shared channel (HS-DSCH) and high speed shared control channel (HS-SCCH) codes of the Node B;
transmitting at least the HS-DSCH and HS-SCCH codes at a power level that does not exceed the maximum transmit power level for HS-DSCH and HS-SCCH codes of the Node B; and
transmitting an Iub signal to the RNC indicating a power associated with the HS-DSCH.
5. The method of claim 4 further comprising:
scheduling HS-DSCH transmissions to wireless transmitreceive units (WTRUs).
6. A method, performed by a radio network controller (RNC), of providing high speed downlink packet access (HSDPA) services, the method comprising:
transmitting a first Iub signal to a Node B indicating a maximum transmit power level for all channel codes transmitted by the Node B;
transmitting a second Iub signal to the Node B indicating a maximum transmit power level for high speed downlink shared channel (HS-DSCH) and high speed shared control channel (HS-SCCH) codes of the Node B; and
receiving an Iub signal by the RNC from the Node B indicating a power associated with the HS-DSCH.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit for electrostatic discharge clamping, comprising:
a detection module coupled with a first power line of a first power source and a second power line of the first power source, wherein a third terminal of the detection module is coupled to a first power line of a second power source;
a control module coupled with the first power line of the first power source and the second power line of the first power source, wherein a third terminal of the control module is coupled to a voltage division terminal of the detection module; and
a clamping module coupled with the first power line of the first power source and the second power line of the first power source, wherein a third terminal of the clamping module is coupled to a fourth terminal of the control module;
wherein the voltage division terminal provides a voltage to the control module according to an electrostatic discharge event on the first power line of the first power source, and the control module then controls the clamping module to couple the first power line of the first power source to the second power line of the first power source.
2. The circuit according to claim 1, wherein the detection module is a resistor, a capacitor, a transistor, or a diode.
3. The circuit according to claim 2, wherein the transistor is a bipolar junction transistor or a field effect transistor.
4. The circuit according to claim 1, wherein a first terminal of the detection module is coupled to a first terminal of a first transistor, a third terminal of the first transistor is coupled to a first terminal of a first resistor, a second terminal of the first resistor is coupled to the first power line of the second power source, and a second terminal of the first transistor is coupled to the voltage division terminal.
5. The circuit according to claim 1, wherein the voltage division terminal is connected with a first terminal of a second resistor, and a second terminal of the second resistor is coupled to the second power line of the first power source.
6. The circuit according to claim 1, wherein the control module coupled between the first power line of the first power source and the second power line of the first power source comprises at least two inverters.
7. The circuit according to claim 6, wherein the at least two inverters comprise a first pair of transistors with opposite polarities and a second pair of transistors with opposite polarities, a third terminal of the first pair of transistors is coupled to the voltage division terminal, a second terminal of the first pair of transistors is coupled to a third terminal of the second pair of transistors, and a second terminal of the second pair of transistors is coupled to the third terminal of the clamping module.
8. The circuit according to claim 1, wherein the clamping module is a second transistor which is coupled with the first power line of the first power source and the second power line of the first power source, a third terminal of the second transistor is coupled to the fourth terminal of the control module, and the second transistor is controlled by the control module.
9. The circuit according to claim 8, wherein the detection module comprises a first transistor and a second resistor, a first terminal of the first transistor is coupled with the first power line of the first power source, a third terminal of the first transistor is electrically connected to the first power line of the second power source, the voltage division terminal is coupled with a first terminal of a second resistor and a second terminal of the first transistor, and a second terminal of the second resistor is coupled with the second power line of the first power source; and when the electrostatic discharge event occurs, the first transistor is in an on state and cooperates with the second resistor, to perform voltage division, and after the control module controls the second transistor to be in an on state, the second transistor couples the first power line of the first power source to the second power line of the first power source.
10. The circuit according to claim 1, wherein the detection module comprises a first capacitor and a second capacitor, a first terminal of the first capacitor is coupled to the first power line of the first power source, a second terminal of the second capacitor is coupled to the second power line of the first power source, and a first terminal of the second capacitor coupled to a second terminal of the first capacitor is the voltage division terminal.
11. The circuit according to claim 10, wherein the first capacitor comprises a third transistor, the second capacitor comprises a fourth transistor, polarities of the third transistor and the fourth transistor are opposite, a third terminal of the third transistor coupled to a third terminal of the fourth transistor is the voltage division terminal, a first and a second terminal of the third transistor are coupled to the first power line of the first power source, a first and a second terminal of the fourth transistor are coupled to the second power line of the first power source.
12. The circuit according to claim 10, wherein the voltage division terminal is coupled to a second terminal of a fifth transistor, a first terminal of the fifth transistor is coupled to the first power line of the second power source, and a third terminal of the fifth transistor is coupled to the second power line of the first power source through a third resistor.
13. The circuit according to claim 12, wherein the control module is at least one inverter.
14. The circuit according to claim 13, wherein the inverter comprises a third pair of transistors with opposite polarities, a second terminal of the third pair of transistors is coupled to the third terminal of the clamping module, a third terminal of the third pair of transistors is coupled to the voltage division terminal.
15. The circuit according to claim 12, wherein the clamping module is a second transistor, when the electrostatic discharge event occurs, the fifth transistor is in an off state and cooperates with the first capacitor and the second capacitor to perform voltage division, and after the control module controls the second transistor to be in an on state, the second transistor couples the first power line of the first power source to the second power line of the first power source.
16. The circuit according to claim 10, wherein the voltage division terminal is coupled to a second terminal of a sixth transistor, a third terminal of the sixth transistor is coupled to a terminal of a fourth resistor, another terminal of the fourth resistor is coupled to the first power line of the second power source, and a first terminal of the sixth transistor is coupled to the second power line of the first power source.
17. The circuit according to claim 16, wherein the clamping module is a second transistor, when the electrostatic discharge event occurs, the sixth transistor is in an off state and cooperates with the first capacitor and the second capacitor to perform voltage division, and after the control module controls the second transistor to be in an on state, the second transistor couples the first power line of the first power source to the second power line of the first power source.
18. The circuit according to claim 1, wherein at least one diode is connected with the first power line of the second power source in series, in order to decrease a voltage difference between a first terminal and a third terminal of a transistor in the detection module.
19. The circuit according to claim 1, wherein the control module is electrically connected to the first power line of the first power source through at least one diode, in order to decrease the voltage received by the control module from the first power source.
20. A method for electrostatic discharge clamping, comprising the following steps:
generating a voltage on a voltage division terminal of a detection module according to an electrostatic discharge event on a first power line of a first power source; and
providing the voltage to a control module for controlling a clamping module;
wherein a third terminal of the detection module is coupled to a first power line of a second power source, and when the control module is driven by the voltage to control the clamping module to be in an on state, the first power line of the first power source couples to a second power line of the first power source.
21. The method according to claim 20, wherein the voltage on the voltage division terminal of a detection module is generated by using resistors or capacitors.