1. A mold release layer comprising the hydrosilylation reaction product between a hydrogen-terminated silicon surface and at least one compound selected from the group consisting of fluorinated terminal alkenes, fluorinated terminal alkynes, and mixtures thereof.
2. The mold release layer of claim 1 wherein said at least one fluorinated terminal alkene is represented by the formula R1\u2014CX\u2550CH2, where R1 is a perfluorinated alkyl group, optionally including at least one unsaturated bond, and where X is H or F.
3. The mold release layer of claim 1 wherein said at least one fluorinated terminal alkyne is represented by the formula R2\u2014C\u2261CH, where R2 is a perfluorinated alkyl group, optionally including at least one unsaturated bond.
4. The mold release layer of claim 1 wherein said at least one fluorinated terminal alkene is represented by the formula R1\u2014CH\u2550CH2, where R1 is a perfluorinated alkyl group, and wherein said at least one fluorinated terminal alkyne is represented by the formula R2\u2014CH\u2261CH, where R2 is a perfluorinated alkyl group, where R1 is the same as or different than R2.
5. A mold for nanometer scale imprint lithography having a silicon surface and provided with a mold release layer comprising the hydrosilylation reaction product between a hydrogen-terminated silicon surface and at least one compound selected from the group consisting of fluorinated terminal alkenes, fluorinated terminal alkynes, and mixtures thereof.
6. The mold of claim 5 wherein said mold comprises silicon, thereby providing said silicon surface.
7. The mold of claim 5 wherein a layer of silicon is formed on said mold, thereby providing said silicon surface.
8. The mold of claim 5 wherein said at least one fluorinated terminal alkene is represented by the formula R1\u2014CX\u2550CH2, where R1 is a perfluorinated alkyl group, optionally including at least one unsaturated bond, and X is H or F.
9. The mold of claim 5 wherein said at least one fluorinated terminal alkyne is represented by the formula R2\u2014C\u2261CH, where R2 is a perfluorinated alkyl group, optionally including at least one unsaturated bond.
10. The mold of claim 5 wherein said at least one fluorinated terminal alkene is represented by the formula R1\u2014CH\u2550CH2, where R1 is a perfluorinated alkyl group, and wherein said at least one fluorinated terminal alkyne is represented by the formula R2\u2014CH\u2261CH, where R2 is a perfluorinated alkyl group, where R1 is the same as or different than R2.
11. The mold of claim 5 wherein said mold is a thermal imprint mold.
12. The mold of claim 11 wherein said mold comprises a silicon wafer.
13. The mold of Clam 5 wherein said mold is a step and flash imprint lithography mold.
14. The mold of claim 13 wherein said mold comprises fused silica glass.
15. The mold of claim 14 wherein a surface of said fused silica glass is coated with a layer of silicon.
16. The mold of claim 15 wherein said layer of silicon comprises amorphous silicon.
17. A method of forming a mold release layer on a mold for nanometer scale imprint lithography, said method comprising
providing said mold having a silicon surface thereon;
creating a hydrogen-terminated surface on said silicon surface; and
forming a hydrosilylation reaction product by reacting said hydrogen-terminated silicon surface on said mold with at least one compound selected from the group consisting of fluorinated terminal alkenes, fluorinated terminal alkynes, and mixtures thereof to thereby form said mold release layer comprising said hydrosilylation reaction product.
18. The method of claim 17 wherein said at least one fluorinated terminal alkene is represented by the formula R1\u2014CX\u2550CH2, where R1 is a perfluorinated alkyl group, optionally including at least one unsaturated bond, and X is H or F.
19. The method of claim 17 wherein said at least one fluorinated terminal alkyne is represented by the formula R2\u2014C\u2261CH, where R2 is a perfluorinated alkyl group, optionally including at least one unsaturated bond.
20. The method of claim 17 wherein said at least one fluorinated terminal alkene is represented by the formula R1\u2014CH\u2550CH2, where R1 is a perfluorinated alkyl group, and wherein said at least one fluorinated terminal alkyne is represented by the formula R2\u2014CH\u2261CH, where R2 is a perfluorinated alkyl group, where R1 is the same as or different than R2.
21. The method of claim 17 wherein said mold is a thermal imprint mold.
22. The method of claim 21 wherein said mold comprises a silicon wafer.
23. The method of clam 17 wherein said mold is a step and flash imprint lithography mold.
24. The method of claim 23 wherein said mold comprises fused silica glass.
25. The method of claim 24 wherein a surface of said fused silica glass is coated with a layer of silicon.
26. The method of claim 25 wherein said layer of silicon comprises amorphous silicon.
27. The method of claim 17 wherein said hydrogen-terminated silicon surface is created by etching said silicon surface with a buffered oxide etch.
28. The method of claim 27 wherein said buffered oxide etch comprises a solution of HF, NH4F, and water.
29. The method of claim 17 wherein said hydrogen-terminated silicon surface is reacted with said at least one compound by light-stimulated hydrosilylation, thermally-stimulated hydrosilylation, Lewis acid catalyzed reaction, or carbocation-initiated hydride abstraction.
30. The method of claim 29 wherein said light-stimulated hydrosilylation is performed by the steps of:
exposing said hydrogen-terminated silicon surface of said mold to either a vapor or a liquid solution containing a fluorinated terminal alkene or alkyne;
exposing said silicon surface to light;
rinsing said silicon surface and optionally repeating at least one of the preceding steps at least once;
rinsing and sonicating said silicon surface in an appropriate solvent to remove any non-covalently bonded absorbates; and
optionally, heat-treating said silicon surface to crosslink adjacent molecules bonded to said silicon surface.
31. The method of claim 30 wherein said liquid solution is employed, comprising a solution of said fluorinated terminal alkene or alkyne in a fluorinated solvent.
32. The method of claim 30 wherein said exposing to light is performed using a flux of up to 100 mWcm2 for a period of time of up to 30 minutes.
33. The method of claim 29 wherein said thermally stimulated hydrosilylation is performed by:
exposing said silicon surface to either a vapor or a liquid solution containing a fluorinated terminal alkene or alkyne;
exposing said silicon surface to heat;
rinsing said silicon surface and optionally repeating at least one of the preceding steps at least once;
rinsing and sonicating said silicon surface in an appropriate solvent to remove any non-covalently bonded absorbates; and
optionally, heat-treating said silicon surface to crosslink adjacent molecules bonded to said silicon surface.
34. The method of claim 33 wherein said liquid solution is employed, comprising a solution of said fluorinated terminal alkene or alkyne in a fluorinated solvent.
35. The method of claim 33 wherein said exposing to heat is performed using a temperature of 40\xb0 to 100\xb0 C. for a period of time of up to one hour.
36. The method of claim 29 wherein said Lewis acid catalyzed reaction is performed by:
exposing said silicon surface to a liquid solution containing a fluorinated terminal alkene or alkyne and a Lewis acid catalyst;
rinsing said silicon surface and optionally repeating the preceding step at least once;
rinsing and sonicating said silicon surface in an appropriate solvent to remove any noncovalently bonded absorbates; and
optionally, heat-treating said silicon surface to crosslink adjacent molecules bonded to said silicon surface.
37. The method of claim 36 wherein said liquid solution comprises a solution of said fluorinated terminal alkene or alkyne in a fluorinated solvent.
38. The method of claim 36 wherein said exposing step is performed by sequentially exposing said silicon surface to a first liquid solution comprising said Lewis acid catalyst followed by exposing said silicon surface to a second liquid solution comprising said fluorinated terminal alkene or alkyne in solution.
39. The method of claim 29 wherein said carbocation-initiated hydride abstraction is performed by:
exposing said silicon surface to a liquid solution containing a fluorinated terminal alkene or alkyne and a hydride-extracting carbocation species;
rinsing said silicon surface and optionally repeating the preceding step at least once;
rinsing and sonicating said silicon surface in an appropriate solvent to remove any noncovalently bonded absorbates; and
optionally heat-treating said silicon surface to crosslink adjacent molecules bonded to the surface.
40. The method of claim 39 wherein said liquid solution comprises a solution of said fluorinated terminal alkene or alkyne in a fluorinated solvent.
41. The method of claim 39 wherein said exposing step is performed by sequentially exposing said silicon surface to a first liquid solution comprising said hydride extracting carbocation solution followed by exposing said silicon surface to a second liquid solution comprising said fluorinated terminal alkene or alkyne in solution.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a substrate comprising a plurality of fins, wherein each of the plurality of fins is separated by one of a plurality of row trenches formed in the substrate; and
a first plurality of gate trenches, wherein each of the first plurality of gate trenches is formed over a portion of a respective one of the plurality of fins and a portion of a respective one of the plurality of row trenches, and wherein each of the first plurality of gate trenches comprises a first conductor disposed therein; and
a second plurality of gate trenches, wherein each of the second plurality of gate trenches is only formed over a portion of a respective one of the plurality of fins and not over a row trench.
2. The device of claim 1, wherein the first conductor comprises tungsten or ruthenium.
3. The device of claim 1, wherein each of the first plurality of gate trenches comprises a gate oxide formed therein, below the first conductor.
4. The device of claim 3, wherein the gate oxide comprises silicon dioxide or oxynitride.
5. The device of claim 1, wherein each of the plurality of row trenches is filled with an oxide.
6. The device of claim 1, wherein each first conductor comprises a gate and each pair of gates comprises access lines of a respective one of the plurality of fins.
7. The device of claim 1, wherein each of the second plurality of gate trenches comprises a gate oxide formed therein.
8. A semiconductor device, comprising:
a substrate comprising a plurality of fins, wherein each of the plurality of fins is separated by one of a plurality of row trenches formed in the substrate; and
a first plurality of gate trenches, wherein each of the first plurality of gate trenches is formed over a portion of a respective one of the plurality of fins and a portion of a respective one of the plurality of row trenches, and wherein each of the first plurality of gate trenches comprises:
a first conductor disposed therein;
a gate oxide disposed therein below the first conductor; and
a liner formed therein, on the gate oxide.
9. The device of claim 8, wherein the liner comprises titanium nitride or tungsten nitride.
10. A semiconductor device, comprising:
a substrate comprising a plurality of fins, wherein each of the plurality of fins is separated by one of a plurality of row trenches formed in the substrate; and
a first plurality of gate trenches, wherein each of the first plurality of gate trenches is formed over a portion of a respective one of the plurality of fins and a portion of a respective one of the plurality of row trenches, and wherein each of the first plurality of gate trenches comprises:
a first conductor disposed therein; and
a second plurality of gate trenches, wherein each of the second plurality of gate trenches is only formed over a portion of a respective one of the plurality of fins, wherein each of the second plurality of gate trenches comprises:
a gate oxide formed therein and
a liner formed therein, on the gate oxide.
11. The device of claim 10, wherein each of the second plurality of gate trenches comprises a second conductor formed therein, on the liner.
12. The device of claim 11, wherein each second conductor comprises a gate and wherein each gate comprises a grounded gate of a respective one of the plurality of fins.
13. A semiconductor device, comprising:
a plurality of row trenches defining a plurality of fin field-effect transistors (finFETs);
a first plurality of gate trenches in a substrate, wherein each of the first plurality of gate trenches is formed over a portion of a respective one of the plurality of finFETs and a portion of a respective one of the plurality of row trenches; and
a second plurality of gate trenches in the substrate, wherein each of the second plurality of gate trenches is only formed over a portion of a respective one of the plurality of finFETs and not over any row trench of the plurality of row trenches.
14. The device of claim 13, wherein each of the second plurality of gate trenches includes a grounded gate formed therein.
15. The device of claim 13, wherein each of the first plurality of gate trenches includes an access line formed therein.
16. The device of claim 13, wherein the device comprises a 6F2 architecture.
17. A semiconductor device, comprising:
a plurality of fins formed in a substrate;
a plurality of row trenches, extending parallel to and between the plurality of fins, wherein each of the plurality of row trenches is filled with a dielectric material; and
a plurality of gate trenches, extending parallel to and between the plurality of fins, wherein all surfaces of each of the plurality of gate trenches are coated with a gate dielectric, and wherein each of the plurality of gate trenches comprises a conductor formed therethrough, wherein the gate dielectric is planar with the plurality of fins and formed through planarization.
18. The semiconductor device of claim 17, wherein the dielectric material in each of the plurality of row trenches comprises a top portion and a bottom portion, and wherein a width of the top portion is less than a width of the bottom portion.
19. The semiconductor device of claim 17, wherein each of the plurality of gate trenches is formed only over a portion of a respective one of the plurality of row trenches and not over a row trench.
20. A semiconductor device, comprising:
a plurality of fins formed in a substrate;
a plurality of row trenches, extending parallel to and between the plurality of fins, wherein each of the plurality of row trenches is filled with a dielectric material;
a plurality of gate trenches, extending parallel to and between the plurality of fins, wherein all surfaces of each of the plurality of gate trenches are coated with a gate dielectric, and wherein each of the plurality of gate trenches comprises a conductor formed therethrough; and a liner formed between the gate dielectric and the conductor in each of the plurality of gate trenches.
21. The semiconductor device of claim 17, comprising twice as many of the plurality of gate trenches as the plurality of row trenches.
22. The semiconductor device of claim 17, comprising three times as many of the plurality of gate trenches as the plurality of row trenches.
23. The semiconductor device of claim 17, wherein the conductor in each of the plurality of gate trenches forms a respective access line.
24. The semiconductor device of claim 17, wherein a first number of the conductor in each of the plurality of gate trenches forms a respective access line, and wherein a second number of the conductor in each of the plurality of gate trenches forms a respective grounded gate.
25. The semiconductor device of claim 24, wherein the first number is two times the second number.