1. An electronic apparatus for operably coupling to at least a first device of a variety of devices having at least one connector thereon, the apparatus comprising:
a variety of connectors, wherein the variety of connectors include a first connector that connects to the at least one connector;
a programmable coupler having an input for receiving coupling instructions and having communication ports coupled to the variety of connectors, wherein at least one of the communication ports is coupled to the first connector, the programmable coupler for coupling the at least one communication port in accordance with the coupling instructions;
a controller coupled to the programmable coupler, the controller for determining that the first device is connected to the first connector, and for providing the coupling instructions, the controller for accessing a first device driver of a variety of device drivers, and accessing a first connector core of a variety of connector cores, and the controller being coupled to provide the first device driver and the first connector core; and
a programmable logic unit coupled to the controller and the programmable coupler, and the programmable logic unit having a variety of logic resources, the programmable logic unit for receiving the first device driver and the first connector core, for configuring at least some of the variety of logic resources in accordance with the first connector core to provide a first connector processor and first device driver and the, and for configuring the first device driver to operate with the connector processor, wherein the first device driver and the first connector processor establish communication with the first device via the programmable coupler.
2. An electronic apparatus in accordance with claim 1, further comprising:
a memory having at least another connector thereon, wherein the variety of connectors include a second connector that couples to the at least another connector, the memory having at least a device driver portion and a connector core portion.
3. An electronic apparatus in accordance with claim 2 wherein the memory comprises a semiconductor memory.
4. An electronic apparatus in accordance with claim 3 wherein the semiconductor memory comprises one or more random access memory, dynamic random access memory, read only memory, programmable read only memory.
5. An electronic apparatus in accordance with claim 2 wherein the memory comprises a magnetic memory.
6. An electronic apparatus in accordance with claim 5 wherein the magnetic memory comprises a hard disk drive.
7. An electronic apparatus in accordance with claim 6 wherein second connector and the at least another connector comprises matching IDE connectors.
8. An electronic apparatus in accordance with claim 2 wherein the memory comprises optical memory.
9. An electronic apparatus in accordance with claim 8 wherein the optical memory comprises a readwrite optical disk drive.
10. An electronic apparatus in accordance with claim 1 wherein the controller comprises at least one microprocessor.
11. An electronic apparatus in accordance with claim 10 wherein the controller comprises at least one memory coupled to the at least one microprocessor.
12. An electronic apparatus in accordance with claim 11 wherein the at least one memory includes at least a device driver portion and a connector core portion.
13. An electronic apparatus in accordance with claim 1 wherein the programmable coupler comprises at least another programmable logic unit.
14. An electronic apparatus in accordance with claim 1 wherein the programnmable coupler comprises at least one matrix switching device.
15. An electronic apparatus in accordance with claim 1 wherein the programmable coupler comprises at least one multiplexer.
16. An electronic apparatus in accordance with claim 1 wherein the programmable logic unit comprises a programmable logic device, a programmable logic array, or a field programmable gate array.
17. An electronic apparatus in accordance with claim 1 wherein the variety of connectors comprise a plurality of at least one of the variety of connectors.
18. An electronic apparatus in accordance with claim 1 wherein the variety of connectors includes one or more of the following connectors: an IDE connector, a USB connector, an audio connector, a video connector, a serial connector, a parallel connector, a Firewire connector, a PCI connector and a PCMCIA connector.
19. An electronic apparatus in accordance with claim 18 wherein the first memory further comprises an application portion for storing a variety of application programs that operate with at least some of the variety of device drivers and some of the variety of connector cores to support the exchange of services with at least some of the variety of devices.
20. An electronic apparatus for operably coupling to at least a first device of a variety of devices having at least one connector thereon, the apparatus comprising:
a variety of connectors, wherein the variety of connectors include a first connector that physically connects to the at least one connector;
a first memory having a device driver portion for storing a variety of device drivers and having a connector core portion for storing a variety of connector cores;
a programmable logic device having communication ports coupled to the variety of connectors; and
a controller coupled to the first memory and the programmable logic device, the controller for communicating with the programmable logic device to determine the first device is connected to the first connector, and the controller for providing at least a first device driver of the variety of device drivers and at least a first connector core of the variety of connector cores from the first memory to the programmable logic device, wherein the programmable logic device configures a corresponding connector processor therein and configures a corresponding device driver to operate with the connector processor, and wherein the corresponding device driver and the corresponding connector processor establish communication with the first device through the first connector.
21. An electronic apparatus in accordance with claim 20 wherein the first memory further comprises an operating system portion and a program portion.
22. An electronic apparatus in accordance with claim 21 wherein the program portion includes a main program portion, an initialization program portion and a power down program portion.
23. An electronic apparatus in accordance with claim 20 further comprising a second memory coupled to the controller and coupled to the programmable logic device, the second memory for providing working storage for the controller andor the programmable logic device.
24. An electronic apparatus in accordance with claim 23 wherein the second memory includes at least a flash memory, a static random access memory (SRAM), or a dynamic access memory (DRAM).
25. An electronic apparatus in accordance with claim 20 wherein the controller comprises a microcontroller.
26. An electronic apparatus in accordance with claim 20 wherein the first memory comprises at least a flash erasable read-only-memory.
27. An electronic apparatus in accordance with claim 20 wherein the programmable logic unit comprises at least a programmable logic array, or a field programmable gate array.
28. An electronic apparatus in accordance with claim 20 wherein the variety of connectors include one or more of the following connectors: an IDE connector, a USB connector, an audio connector, a video connector, a serial connector, a parallel connector, a Firewire connector, a PCI connector and a PCMCIA connector.
29. A method in a reconfigurable communication interface for operably coupling to a first device of a variety of devices, the first device having at least one connector thereon, the method comprising the steps of:
a) providing the reconfigurable communication interface comprising:
a variety of connectors, wherein the variety of connectors include a first connector that connects to the at least one connector;
a programmable logic device having a plurality of communication ports coupled to the variety of connectors; and
a controller coupled to the programmable logic device;
b) detecting the first device is physically connected to the fist connector;
c) accessing a first connector core of a variety of connector cores associated with the first connector;
d) configuring a first connector processor in the programmable logic device;
e) accessing a first device driver of a variety of device drivers associated with the first device;
f) configuring the first device to operate with the first connector processor in the programmable logic device; and
g) establishing communication with the first device through the first connector using the first connector processor and the first device driver.
30. A method in accordance with claim 29 further comprising the steps of:
h) providing a second device of the variety of devices, the second device having at least another connector thereon, and wherein the variety of connectors include a second connector that connects to the at least another connector;
i) detecting the second device is physically connected to the second connector;
j) accessing a second connector core of the variety of connector cores associated with the second connector;
k) configuring the second connector processor in the programmable logic device;
l) accessing a second device driver of the variety of device drivers associated with the second device;
m) configuring the second device driver to operate with the second connector processor in the programmable logic device; and
n) establishing communication with the second device through the second connector using the second connector processor and the second device driver.
31. A method in accordance with claim 30 further comprising the steps of:
o) detecting the first device is physically disconnected from the first connector;
p) unloading the first connector processor and the first device driver.
32. A method in accordance with claim 29 wherein step (b) comprises the step of detecting whether a first communication port of the plurality of communication ports, which is coupled to the first connector, is active.
33. A method in accordance with claim 32 wherein detecting whether the first communication port is active comprises detecting the status of one or more signals associated with the first communication port.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory device comprising:
a memory element formed over a first substrate, the memory element comprising
a first electrode;
a second electrode; and
a layer containing an organic compound, the layer containing the organic compound being interposed between the first electrode and the second electrode,
a sealing layer formed over the second electrode, the sealing layer containing a moisture absorbing material, and
a flexible substrate formed over the sealing layer containing the moisture absorbing material.
2. A memory device according to claim 1,
wherein the first substrate is flexible.
3. A memory device according to claim 1,
wherein the memory element is arranged to undergo a short circuit when a voltage is applied between the first electrode and the second electrode.
4. A memory device according to claim 1, further comprising an antenna,
wherein the antenna is arranged to receive and transmit data and instruction with radio signals.
5. A memory device according to claim 1,
wherein a thickness of the layer containing the organic compound is in the range from 5 nm to 30 nm.
6. A memory device according to claim 1,
wherein a grain size of the moisture absorbing material is greater than or equal to 1 \u03bcm and less than or equal to 100 \u03bcm.
7. A memory device according to claim 1,
wherein the moisture absorbing material is a particle formed of molten silica, crystalline silica, alumina, silicon nitride, aluminum nitride, boron nitride, zeolite, an oxide of an alkaline earth metal, sulfate or a high water-absorbing polymer.
8. A memory device comprising:
a thin film transistor formed over a first substrate,
a memory element electrically connected to the thin film transistor, the memory element comprising
a first electrode;
a second electrode; and
a layer containing an organic compound, the layer containing the organic compound being interposed between the first electrode and the second electrode,
a sealing layer formed over the second electrode, the sealing layer containing a moisture absorbing material, and
a flexible substrate formed over the sealing layer containing the moisture absorbing material.
9. A memory device according to claim 8,
wherein the first substrate is flexible.
10. A memory device according to claim 8,
wherein the memory element is arranged to undergo a short circuit when a voltage is applied between the first electrode and the second electrode.
11. A memory device according to claim 8, further comprising an antenna,
wherein the antenna is electrically connected to the thin film transistor.
12. A memory device according to claim 8,
wherein a thickness of the layer containing the organic compound is in the range from 5 nm to 30 nm.
13. A memory device according to claim 8,
wherein a grain size of the moisture absorbing material is greater than or equal to 1 \u03bcm and less than or equal to 100 \u03bcm.
14. A memory device according to claim 8,
wherein the moisture absorbing material is a particle formed of molten silica, crystalline silica, alumina, silicon nitride, aluminum nitride, boron nitride, zeolite, an oxide of an alkaline earth metal, sulfate or a high water-absorbing polymer.
15. A memory device comprising:
a memory element formed over a first substrate, the memory element comprising
a first electrode;
a second electrode; and
a layer containing a buffer layer and a layer containing an organic compound, the layer containing the buffer layer and the layer containing the organic compound being interposed between the first electrode and the second electrode,
a sealing layer formed over the second electrode, the sealing layer containing a moisture absorbing material, and
a flexible substrate formed over the sealing layer containing the moisture absorbing material.
16. A memory device according to claim 15,
wherein the first substrate is flexible.
17. A memory device according to claim 15,
wherein the memory element is arranged to undergo a short circuit when a voltage is applied between the first electrode and the second electrode.
18. A memory device according to claim 15, further comprising an antenna,
wherein the antenna is arranged to receive and transmit data and instruction with radio signals.
19. A memory device according to claim 15,
wherein a thickness of the layer containing the organic compound is in the range from 5 nm to 30 nm.
20. A memory device according to claim 15,
wherein a grain size of the moisture absorbing material is greater than or equal to 1 \u03bcm and less than or equal to 100 \u03bcm.
21. A memory device according to claim 15,
wherein the moisture absorbing material is a particle formed of molten silica, crystalline silica, alumina, silicon nitride, aluminum nitride, boron nitride, zeolite, an oxide of an alkaline earth metal, sulfate or a high water-absorbing polymer.
22. A memory device according to claim 15,
wherein the buffer layer comprises a material selected from a metal oxide, a metal halide, a metal carbonate, a metal sulfide, or a metal nitrate.
23. A manufacturing method for a memory device comprising a memory element, the manufacturing method comprising the step of:
forming a peeling layer over a first substrate,
forming a first electrode over the peeling layer,
forming a layer containing an organic compound over the first electrode,
forming a second electrode over the layer containing the organic compound,
forming a sealing layer over the second electrode, wherein the sealing layer contains a moisture absorbing material, and
peeling off the layer containing the first electrode, the layer containing the organic compound, the second electrode, and the sealing layer from the first substrate.
24. A manufacturing method for a memory device according to claim 23, further comprising the step of forming a second substrate and the third substrate so that the layer containing first electrode, the layer containing the organic compound, the second electrode, and the sealing layer is interposed between the second substrate and the third substrate,
wherein the second substrate and the third substrate are flexible.
25. A manufacturing method for a memory device comprising a memory element, the manufacturing method comprising the step of:
forming a peeling layer over a first substrate,
forming a first electrode over the peeling layer,
forming a layer containing an organic compound over the first electrode,
forming a second electrode over the layer containing the organic compound,
forming a sealing layer over the second electrode, wherein the sealing layer contains a moisture absorbing material,
peeling off the layer containing the first electrode, the layer containing the organic compound, the second electrode, and the sealing layer from the first substrate,
forming a second flexible substrate so that the layer containing the first electrode, the layer containing the organic compound, and the second electrode is interposed between the second substrate and the sealing layer,
providing the layer containing the second flexible substrate, the first electrode, the layer containing the organic compound, the second electrode, and the sealing layer onto a third flexible substrate, wherein the third flexible substrate is arranged to be fed from a first supply roll and be collected by a collection roll, and
forming a fourth flexible substrate so that the layer containing the second substrate, the first electrode, the layer containing the organic compound, the second electrode, and the sealing layer is interposed between the third flexible substrate and the fourth flexible substrate, wherein the fourth flexible substrate is arranged to be fed from a second supply roll and be collected by the collection roll.