1. A capacitor comprising:
a lower electrode formed through at least one interlayer dielectric layer on a semiconductor substrate and through a portion of the semiconductor substrate, wherein an upper surface of the lower electrode has the same height as that of the interlayer dielectric layer;
a dielectric layer coating an inner sidewall and a bottom of the lower electrode, and a portion of the interlayer dielectric layer around a top of the lower electrode; and
an upper electrode on the dielectric layer.
2. A method of forming a capacitor comprising:
forming at least one interlayer dielectric layer on a semiconductor substrate;
sequentially etching the at least one interlayer dielectric layer and a portion of the semiconductor substrate to form a storage node hole;
conformally forming a lower electrode layer in the storage node hole and on the interlayer dielectric layer;
performing a planarization process to remove a portion of the lower electrode layer that lies on the interlayer dielectric layer and to form a lower electrode in the storage node;
sequentially forming a dielectric layer and an upper electrode layer on the lower electrode; and
sequentially patterning the upper electrode layer and dielectric layer.
3. The method of claim 2, after forming the storage node hole, further comprising performing an ion implantation process in a region of the semiconductor substrate exposed by the storage node hole at least once.
4. A DRAM device comprising:
a first well having a first depth in a semiconductor substrate;
a second well having a second depth shallower than the first depth in the first well;
a device isolation layer in the semiconductor substrate to define an active region;
a gate pattern formed on the semiconductor substrate;
a first impurity implantation region being formed in the active region at both sides of the gate pattern and having a third depth shallower than the second depth;
at least one interlayer dielectric layer covering the gate pattern and the semiconductor substrate;
a cup-shaped lower electrode formed through the at least one interlayer dielectric layer and through a portion of the semiconductor substrate, the cup-shaped electrode located at one side of the gate pattern, wherein an upper surface of the lower electrode has the same height as that of the interlayer dielectric layer;
a dielectric layer coating an inner sidewall and a bottom of the lower electrode, and a portion of the interlayer dielectric layer around a top of the lower electrode; and
an upper electrode on the dielectric layer.
5. The DRAM device of claim 4, wherein a lowermost surface of the lower electrode is positioned in the substrate shallower than the first depth and deeper than the second depth.
6. The DRAM device of claim 5, further comprising:
a second impurity implantation region formed in the semiconductor substrate in contact with the lower electrode below the second depth; and
a third impurity implantation region formed in the semiconductor substrate in contact with the lower electrode below the third depth and formed in the second impurity implantation region and the second well,
wherein the first well, the first impurity implantation region, and the third impurity implantation region are doped with impurities of a first type, and
wherein the second well and the second impurity implantation region are doped with impurities of a second type.
7. The DRAM device of claim 4, wherein a lowermost surface of the lower electrode is positioned in the substrate shallower than the second depth and deeper than the third depth.
8. The DRAM device of claim 7, further comprising a second impurity implantation region formed in the semiconductor substrate in contact with the lower electrode below the third depth,
wherein the first well, the first impurity implantation region, and the second impurity implantation region are doped with impurities of a first type, and
wherein the second well is doped with impurities of a second type.
9. The DRAM device of claim 4, further comprising:
an upper interlayer dielectric layer located on the upper electrode and the at least one interlayer dielectric layer;
a bit line contact plug formed through the upper interlayer dielectric layer and the at least one interlayer dielectric layer between neighboring two gate patterns and in contact with the semiconductor substrate; and
a bit line located on the upper interlayer dielectric layer and in contact with the bit line contact plug.
10. The DRAM device of claim 4, further comprising:
a bit line located lower than a height of an upper surface of the lower electrode in the at least one interlayer dielectric layer, and separated from the lower electrode; and
a bit line contact plug connecting the bit line to the semiconductor substrate.
11. A method of forming a DRAM device comprising:
forming a first well having a first depth in a semiconductor substrate;
forming a second well having a second depth shallower than the first depth in the semiconductor substrate;
forming a device isolation layer in the semiconductor substrate to define an active region;
forming a gate pattern on the semiconductor substrate;
forming a first impurity implantation region having a third depth shallower than the second depth in the active region at both sides of the gate pattern;
forming at least one interlayer dielectric layer on the semiconductor substrate;
sequentially patterning the at least one interlayer dielectric layer at one side of the gate pattern and a portion of the semiconductor substrate to form a storage node hole;
conformally forming a lower electrode layer in the storage node hole and on the interlayer dielectric layer;
performing a planarization process to remove a portion of the lower electrode layer that lies on the interlayer dielectric layer and to form a lower electrode in the storage node hole;
sequentially forming a dielectric layer and an upper electrode layer on the lower electrode; and
sequentially patterning the upper electrode layer and the dielectric layer.
12. The method of claim 11, after forming the storage node hole, further comprising performing an ion implantation process in a region of the semiconductor substrate exposed by the storage node hole at least once.
13. The method of claim 11, wherein a bottom of the storage node hole is located in the substrate at a position that is shallower than the first depth and deeper than the second depth.
14. The method of claim 13, after forming the storage node hole, further comprising:
performing an ion implantation process to form a second impurity implantation region in the semiconductor substrate exposed by the storage node hole below the second depth; and
performing an ion implantation process to form a third impurity implantation region in the second well and the second impurity implantation region exposed by the storage node hole below the third depth.
15. The method of claim 13, after forming the storage node hole, further comprising:
performing an ion implantation process to form a third impurity implantation region in the semiconductor substrate exposed by the storage node hole below the third depth; and
performing an ion implantation process to form a second impurity implantation region in the semiconductor substrate exposed by the storage node hole below the second depth,
wherein the second impurity implantation region is formed to surround the third impurity implantation region.
16. The method of claim 14, wherein the first well, the first impurity implantation region, and the third impurity implantation region are doped with impurities of a first type, and
wherein the second well and the second impurity implantation region are doped with impurities of a second type.
17. The method of claim 11, wherein a bottom of the storage node hole is positioned in the substrate at a position that is shallower than the second depth and deeper than the third depth.
18. The method of claim 17, after forming the storage node hole, further comprising performing an ion implantation process to form a second impurity implantation region in the semiconductor substrate exposed by the storage node hole below the third depth,
wherein the first well, the first ion implantation region, and the second impurity implantation region are doped with impurities of a first type,
wherein the second well is doped with impurities of a second type.
19. The method of claim 11, further comprising:
forming an upper interlayer dielectric layer on the semiconductor substrate having the upper electrode;
forming a bit line contact plug formed through the upper interlayer dielectric layer and the at least one interlayer dielectric layer between neighboring two gate patterns and in contact with the semiconductor substrate; and
forming a bit line in contact with the bit line contact plug on the upper interlayer dielectric layer.
20. The method of claim 11, wherein forming the at least one interlayer dielectric layer comprises forming a first interlayer dielectric and forming a second interlayer dielectric, and before forming the second interlayer dielectric and subsequent to forming the first interlayer dielectric, further comprising:
forming a bit line contact plug in contact with the semiconductor substrate through the first interlayer dielectric layer; and
forming a bit line in contact with the bit line contact plug on the first interlayer dielectric layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A substrate liquid processing apparatus comprising:
a substrate holding table configured to hold a substrate;
a rotary driving unit configured to rotate the substrate holding table;
a process-liquid supply unit configured to supply a process-liquid to the substrate held by the substrate holding table;
a guide rotary cup provided around the substrate holding table, the guide rotary cup being configured to rotate together with the substrate holding table to guide the process-liquid scattering from the rotating substrate; and
a guide cup provided around the guide rotary cup, the guide cup being configured to guide downward the process-liquid guided by the guide rotary cup,
wherein the guide cup includes a guide cup body, a downward extension portion extending downward from an inner peripheral end portion of the guide cup body, and an inner peripheral extension portion extending inward from the inner peripheral end portion more than the downward extension portion, the inner peripheral extension portion being configured to form a gas guide space together with the guide rotary cup and the downward extension portion so that a gas turning by the rotation of the guide rotary cup is guided downward.
2. The substrate liquid processing apparatus according to claim 1,
wherein the process-liquid supply unit is configured to selectively supply a plurality of types of process-liquids,
the substrate liquid processing apparatus further comprises: a second guide cup provided below the guide cup, the second guide cup being configured to guide downward the corresponding process-liquid guided by the guide rotary cup; and
an up-down movement driving unit configured to move up and down the second guide cup with respect to the guide cup,
wherein the downward extension portion of the guide cup closes an opening of the guide cup when the process-liquid is guided by the second guide cup.
3. The substrate liquid processing apparatus according to claim 2, further comprising a third guide cup provided below the second guide cup, the third guide cup being configured to guide downward the corresponding process-liquid guided by the guide rotary cup,
wherein the third guide cup is configured to be able to be moved up and down together with the second guide cup, and
a gap between the guide cup and the second guide cup is blocked when the process-liquid is guided by the third guide cup, and the downward extension portion of the guide cup closes an opening of the second guide cup.
4. The substrate liquid processing apparatus according to claim 2,
wherein an up-down moving groove is provided at an outer peripheral end portion of the guide cup body,
the second guide cup and the up-down movement driving unit are connected to each other by a connection member, and
the connection member is configured to be able to be moved up and down in the up-down moving groove.
5. The substrate liquid processing apparatus according to claim 2,
wherein the guide cup body includes a sloped portion extending obliquely downward and outward and a vertical portion extending downward in a vertical direction from an outer peripheral end portion of the sloped portion, and
the second guide cup is configured to be able to be moved up and down in a space between the downward extension portion of the guide cup and the vertical portion of the guide cup body.
6. The substrate liquid processing apparatus according to claim 1,
wherein a cross-section from the inner peripheral extension portion of the guide cup to the downward extension portion is formed in a reverse U-shape.
7. The substrate liquid processing apparatus according to claim 1,
wherein a gap portion is formed between an outer peripheral end portion of the guide rotary cup and an outer peripheral end portion of the substrate holding table so that the process-liquid scattering from the substrate passes through the gap portion, and
a lower end portion of the downward extension portion of the guide cup is disposed above the gap portion.
8. The substrate liquid processing apparatus according to claim 2,
wherein the vertical positional relationship between the guide rotary cup and the guide cup is maintained constant.