1. A computer-readable medium in which is recorded a document error inference processing program that caused a computer to perform processes, wherein said computer comprises a document data memory unit that memorizes a taxonomy schema in which an item element is defined with a tagged structured language, an instance document which includes a context in which an input value is stored in said item element defined in said taxonomy schema, a display link base which includes a hierarchical structure of said item elements of said instance document in display processing, and a calculation link base which includes a reference relationship and a hierarchical structure of said item elements of said instance document in arithmetic processing, the program caused the computer to perform:
a discrepancy detecting process that calculates an input value of said item element of said instance document based on said hierarchical structure of said calculation link base, compares said calculated value and an input value of said instance document corresponding to the item element of said calculated value, and detects a discrepancy between said calculated value and said input value; and
an error inference process that specifies a calculation tree structure of said calculation link base in which the item element of the calculated value in which said discrepancy is detected is set, specifies a display tree structure of said display link base in which the item element of the input value in which said discrepancy is detected is set, compares said item elements themselves set in each of said calculation tree structure and said display tree structure, and infers an excess or deficiency of an item element which is set only in either said calculation tree structure or said display tree structure and has an input value which is consistent with an absolute value of the difference between said input value and said calculated value as an error of said discrepancy if such an item element exists.
2. The computer-readable medium according to claim 1, wherein said error inference process causes said computer to perform a process that infers an element deficiency error of said calculation link base if an item element set in said display tree structure does not exist in said calculation tree structure and the difference calculated by subtracting said calculated value from said input value is consistent with an input value of an item element of said instance document which does not exist in said calculation tree structure.
3. The computer-readable medium according to claim 1, wherein said error inference process causes said computer to perform a process that infers an element excess error of said calculation link base if an item element set in said calculation tree structure does not exist in said display tree structure and the difference calculated by subtracting said calculated value from said input value is consistent with a value calculated by inverting a sign of an input value of an item element of said instance document which does not exist in said display tree structure.
4. The computer-readable medium according to claim 1, wherein when two or more contexts which should be composed of a same set of item elements are included in said instance document, if an item element set in said calculation tree structure is set in the first context and has an input value which is consistent with the difference calculated by subtracting said calculated value from said input value and the same item element having an input value which is equal to a value calculated by subtracting said calculated value from said input value and inverting a sign is not set in the second context, said error inference process makes said computer perform a process that infers a context error of said item element.
5. The computer-readable medium according to claim 1, wherein said program causes said computer to perform an error inference result output process that outputs information about an item element which is inferred as an error as an error inference result of said error inference process.
6. A document error inference processing device comprising:
a document data memory unit that memorizes a taxonomy schema in which an item element is defined as a tagged structured language, an instance document including a context in which an input value is stored in said item element defined in said taxonomy schema, a display link base including a hierarchical structure of said item elements of said instance document in display processing, and a calculation link base including a reference relationship and a hierarchical structure of said item elements of said instance document in arithmetic processing;
a discrepancy detecting process unit that calculates an input value of said item element of said instance document based on said hierarchical structure of said calculation link base, compares said calculated value and an input value of said instance document corresponding to the item element of said calculated value, and detects a discrepancy between said calculated value and said input value; and
an error inference process unit that specifies a calculation tree structure of said calculation link base in which the item element of the calculated value in which said discrepancy is detected is set, specifies a display tree structure of said display link base in which the item element of the input value in which said discrepancy is detected is set, compares said item elements themselves set in each of said calculation tree structure and said display tree structure, and infers an excess or deficiency of an item element which is set only in either said calculation tree structure or said display tree structure and has an input value which is consistent with an absolute value of the difference between said input value and said calculated value as an error of said discrepancy if such an item element exists.
7. A document error inference processing method performed by a computer comprising a document data memory unit that memorizes a taxonomy schema in which an item element is defined as a tagged structured language, an instance document including a context in which an input value is stored in said item element defined in said taxonomy schema, a display link base including a hierarchical structure of said item elements of said instance document in display processing, a calculation link base including a reference relationship and a hierarchical structure of said item elements of said instance document in arithmetic processing, the method comprising:
a discrepancy detecting process step of calculating an input value of said item element of said instance document based on said hierarchical structure in said calculation link base, comparing said calculated value and an input value of said instance document corresponding to the item element of said calculated value, and detecting a discrepancy between said calculated value and said input value; and
an error inference process step of specifying a calculation tree structure of said calculation link base in which the item element of the calculated value in which said discrepancy is detected is set, specifying a display tree structure of said display link base in which the item element of the input value in which said discrepancy is detected is set, comparing said item elements themselves set in each of said calculation tree structure and said display tree structure, and inferring an excess or deficiency of an item element which is set only in either said calculation tree structure or said display tree structure and has an input value which is consistent with an absolute value of the difference between said input value and said calculated value as an error of said discrepancy if such an item element exists.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An amplifier for amplifying a signal, comprising:
an amplifying transistor coupled to a ground and operable to:
receive a signal; and
amplify the received signal; and
one or more bias components coupled to the amplifying transistor, the one or more bias components operable to provide a bias resistance for the amplifying transistor, the one or more bias components comprising a control modulator coupled in series between the amplifying transistor and the ground, the control modulator operable to:
receive a control signal; and
modulate the amplifying transistor in response to the control signal.
2. The amplifier of claim 1, wherein the one or more bias components are operable to provide the bias resistance for the amplifying transistor by:
decreasing a gate voltage in response to an increase in a drain current, the decrease in the gate voltage operable to stabilize the increase in the drain current; and
increasing the gate voltage in response to a decrease in the drain current, the increase in the gate voltage operable to stabilize the decrease in the drain current.
3. The amplifier of claim 1, further comprising a capacitor coupled in parallel with the control modulator and operable to reduce variation of the amplified signal.
4. The amplifier of claim 1, wherein the control modulator comprises a field effect transistor.
5. The amplifier of claim 1, wherein the one or more bias components further comprises a resistor coupled in series to the control modulator.
6. The amplifier of claim 1, wherein the control signal switches the modulating transistor with respect to the ground.
7. A method for amplifying a signal, comprising:
receiving a signal at an amplifying transistor coupled to a ground;
amplifying the received signal using the amplifying transistor;
providing a bias resistance for the amplifying transistor using one or more bias components coupled to the amplifying transistor;
receiving a control signal at a control modulator of the one or more bias components, the control modulator coupled in series between the amplifying transistor and the ground; and
modulating the amplifying transistor in response to the control signal using control modulator.
8. The method of claim 7, wherein providing the bias resistance for the amplifying transistor further comprises:
decreasing a gate voltage in response to an increase in a drain current, the decrease in the gate voltage operable to stabilize the increase in the drain current; and
increasing the gate voltage in response to a decrease in the drain current, the increase in the gate voltage operable to stabilize the decrease in the drain current.
9. The method of claim 7, further comprising reducing variation of the amplified signal using a capacitor coupled in parallel with the control modulator.
10. The method of claim 7, wherein the control modulator comprises a field effect transistor.
11. The method of claim 7, wherein the one or more bias components further comprises a resistor coupled in series to the control modulator.
12. The method of claim 7, wherein the control signal switches the modulating transistor with respect to the ground.
13. An amplifier for amplifying a signal, comprising:
an amplifying transistor coupled to a ground and operable to:
receive a signal; and
amplify the received signal;
one or more bias components coupled to the amplifying transistor, the one or more bias components operable to provide a bias resistance for the amplifying transistor, the one or more bias components comprising a control modulator coupled in series between the amplifying transistor and the ground, the control modulator operable to:
receive a control signal; and
modulate the amplifying transistor in response to the control signal; and
a capacitor coupled in parallel with the control modulator and operable to reduce variation of the amplified signal.
14. The amplifier of claim 13, wherein the one or more bias components are operable to provide the bias resistance for the amplifying transistor by:
decreasing a gate voltage in response to an increase in a drain current, the decrease in the gate voltage operable to stabilize the increase in the drain current; and
increasing the gate voltage in response to a decrease in the drain current, the increase in the gate voltage operable to stabilize the decrease in the drain current.
15. The amplifier of claim 13, wherein the control modulator comprises a field effect transistor.
16. The amplifier of claim 13, wherein the one or more bias components further comprises a resistor coupled in series to the control modulator.
17. The amplifier of claim 13, wherein the control signal switches the modulating transistor with respect to the ground.
18. A method for amplifying a signal, comprising:
receiving a signal at an amplifying transistor coupled to a ground;
amplifying the received signal using the amplifying transistor;
providing a bias resistance for the amplifying transistor using one or more bias components coupled to the amplifying transistor;
receiving a control signal at a control modulator of the one or more bias components, the control modulator coupled in series between the amplifying transistor and the ground;
modulating the amplifying transistor in response to the control signal using control modulator; and
reducing variation of the amplified signal using a capacitor coupled in parallel with the control modulator.
19. The method of claim 18, wherein providing the bias resistance for the amplifying transistor further comprises:
decreasing a gate voltage in response to an increase in a drain current, the decrease in the gate voltage operable to stabilize the increase in the drain current; and
increasing the gate voltage in response to a decrease in the drain current, the increase in the gate voltage operable to stabilize the decrease in the drain current.
20. The method of claim 18, wherein the control modulator comprises a field effect transistor.
21. The method of claim 18, wherein the one or more bias components further comprises a resistor coupled in series to the control modulator.
22. The method of claim 18, wherein the control signal switches the modulating transistor with respect to the ground.
23. A system for amplifying a signal, comprising:
means for receiving a signal at an amplifying transistor coupled to a ground;
means for amplifying the received signal using the amplifying transistor;
means for providing a bias resistance for the amplifying transistor using one or more bias components coupled to the amplifying transistor;
means for receiving a control signal at a control modulator of the one or more bias components, the control modulator coupled in series between the amplifying transistor and the ground; and
means for modulating the amplifying transistor in response to the control signal using control modulator.
24. An amplifier for amplifying a signal, comprising:
an amplifying transistor coupled to a ground and operable to:
receive a signal; and
amplify the received signal;
one or more bias components coupled to the amplifying transistor, the one or more bias components operable to provide a bias resistance for the amplifying transistor by:
decreasing a gate voltage in response to an increase in a drain current, the decrease in the gate voltage operable to stabilize the increase in the drain current; and
increasing the gate voltage in response to a decrease in the drain current, the increase in the gate voltage operable to stabilize the decrease in the drain current;
the one or more bias components comprising:
a resistor coupled in series to the control modulator; and
a control modulator coupled in series between the amplifying transistor and the ground, the control modulator comprising a field effect transistor and operable to:
receive a control signal; and
modulate the amplifying transistor in response to the control signal, the control signal switching the modulating transistor with respect to the ground; and
a capacitor coupled in parallel with the control modulator and operable to reduce variation of the amplified signal.