We claim:
1. A single use processing substrate, comprising:
a cut resistant surface;
at least one absorbent layer adjacent the cut resistant surface; and
a liquid impervious barrier adjacent the at least one absorbent layer;
wherein the substrate includes a score line disposed across the substrate for separating the substrate into two substrates.
2. The single use processing substrate of claim 1, wherein the cut resistant surface is fluid pervious.
3. The single use processing substrate of claim 2, wherein the cut resistant surface is thermoplastic.
4. The single use processing substrate of claim 3, wherein the cut resistant surface includes a plurality of holes therein.
5. The single use processing substrate of claim 1, wherein the liquid impervious barrier is thermoplastic.
6. The single use processing substrate of claim 1, wherein the score line extends through at least the cut resistant surface.
7. The single use processing substrate of claim 6, wherein the score line also extends through the absorbent layer(s).
8. The single use processing substrate of claim 7, wherein the score line also extends through a portion of the barrier.
9. The single use processing substrate of claim 1, wherein the score line extends fully through the substrate adjacent edges of the substrate to create a tear notch.
10. The single use processing substrate of claim 1, wherein the score line is perpendicular to opposite edges of the substrate.
11. The single use processing substrate of claim 10, wherein the score line extends across a width of the substrate.
12. A single use processing substrate, comprising:
first means for providing a cut resistant surface;
second means disposed adjacent the first means for providing a liquid-absorbent portion;
third means disposed adjacent the second means for providing a liquid-impermeable portion; and
fourth means for separating the substrate into two portions.
13. The single use processing substrate of claim 12, wherein the first means also provides a fluid pervious surface.
14. The single use processing substrate of claim 13, wherein the first means also provides a thermoplastic surface.
15. The single use processing substrate of claim 14, wherein the first means includes a plurality of holes therein.
16. The single use processing substrate of claim 12, wherein the third means is thermoplastic.
17. The single use processing substrate of claim 12, wherein the fourth means includes a score line.
18. The single use processing substrate of claim 17, wherein the score line extends through at least the first means.
19. The single use processing substrate of claim 18, wherein the score line also extends through the second means.
20. The single use processing substrate of claim 19, wherein the score line also extends through a portion of the third means.
21. The single use processing substrate of claim 17, wherein the score line cuts through the whole substrate near edges of the substrate to create a tear notch.
22. The single use processing substrate of claim 17, wherein the score line is perpendicular to opposite edges of the substrate.
23. The single use processing substrate of claim 22, wherein the score line extends across a width of the substrate.
24. A single use processing substrate, comprising:
a cut resistant surface;
at least one absorbent layer adjacent the cut resistant layer; and
a liquid impervious barrier adjacent the at least one absorbent layer;
wherein the substrate includes a lateral fold line disposed along a width of the substrate and a plurality of additional fold lines extending from corners of the substrate.
25. The single use processing substrate of claim 24, wherein the substrate when folded has a trapezoid shape.
26. The single use processing substrate of claim 25, wherein the substrate is provided to consumers in the trapezoid shape.
27. The single use processing substrate of claim 24, wherein the plurality of additional fold lines extend to the lateral fold line.
28. The single use processing substrate of claim 27, wherein the plurality of additional fold lines extend to points where the lateral fold line intersects the cut resistant surface.
29. The single use processing substrate of claim 28, wherein the barrier includes lateral edges and longitudinal edges, and wherein when the lateral edges of the substrate are moved towards one another, the longitudinal edges of the substrate fold inwardly along the plurality of fold lines.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A power source noise measuring device, comprising:
a mutual inductor pair placed inside an integrated circuit, said mutual inductor pair including (i) a first inductor connected to between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to external output terminals; and
a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of a voltage waveform output from the second inductor of said mutual inductor pair via the external output terminals.
2. A power source noise measuring device as set forth in claim 1, further comprising a switching unit which switches between connection and disconnection of the first inductor of said mutual inductor pair to the power source voltages.
3. A power source noise measuring device as set forth in claim 1, further comprising a capacitor which is connected in series to the first inductor of said mutual inductor pair, said capacitor being placed between the power source voltages.
4. A power source noise measuring device comprising:
a first mutual inductor pair placed inside an integrated circuit, said first mutual inductor pair including (i) a first inductor connected between power source voltages of the integrated circuit and (ii) a second inductor arranged opposite the first inductor, the both ends of which second inductor are connected to between external output terminals of the integrated circuit;
a variable power source provided outside the integrated circuit;
a second mutual inductor pair placed inside the integrated circuit, said second mutual inductor pair including a third inductor connected to said variable power source and a fourth inductor arranged opposite the third inductor, the both ends of which fourth inductor are connected to external output terminals of the integrated circuit;
an adjusting unit which adjusts voltage of said variable voltage source in such a manner that a first voltage waveform output from the second inductor of said first mutual inductor pair via external output terminals is the same or approximately the same as a second voltage waveform output from the fourth inductor of said second mutual inductor pair via external output terminals; and
a power source noise measuring unit which measures power source noise of the integrated circuit on the basis of voltage of said variable power source adjusted by said adjusting unit.
5. A power source noise measuring device as set forth in claim 4, wherein said power source noise measuring unit measures amplitude and frequency of the power source noise on the basis of the second voltage waveform which is obtained after voltage of said variable power source is adjusted by said adjusting unit.
6. A power source noise measuring device as set forth in claim 4, further comprising:
a first switching unit which switches between connection and disconnection of the first inductor of said first mutual inductor pair to between the power source voltages; and
a second switching unit having the same construction as that of said first switching unit, said second switching unit switching between connection and disconnection of the third inductor of said second mutual inductor pair to said variable voltage source.
7. A power source noise measuring device as set forth in claim 4, wherein circuit patterns of the first inductor and the second inductor of said first mutual inductor pair are the same as those of the third inductor and the fourth inductor, respectively, of said second mutual inductor pair.
8. A power source noise measuring device as set forth in claim 4, further comprising:
a first capacitor arranged between the power source voltages, said first capacitor being connected in series to the first inductor of said first mutual inductor pair; and
a second capacitor having the same construction as that of said first capacitor, said second capacitor being connected in series to the third inductor of said second mutual inductor pair.
9. A power source noise measuring device as set forth in claim 8, wherein circuit patterns of the first inductor, the first capacitor, and the second inductor of said first mutual inductor pair are the same as those of the third inductor, the second capacitor, and the fourth inductor of said second mutual inductor pair.
10. An integrated circuit having an internal circuit which is connected between power source voltages to operate with supply of the power source voltages, comprising:
a mutual inductor pair including (i) a first inductor connected between power source voltages and (ii) a second inductor placed opposite said first inductor; and
a pair of external output terminals which are connected to the opposite ends, respectively, of the second inductor of said mutual inductor pair, said external output terminal pair outputting outside a voltage waveform induced by mutual induction.
11. An integrated circuit as set forth in claim 10, further comprising a switching unit which switches between connection and disconnection of the first inductor of said mutual inductor pair to between the power source voltages.
12. An integrated circuit as set forth in claim 10, further comprising a capacitor which is connected in series to the first inductor, said capacitor being placed between the power source voltages.
13. An integrated circuit having an internal circuit which is connected between power source voltages to operate with supply of the power source voltages, comprising:
a first mutual inductor pair including (i) a first inductor connected between the power source voltages and (ii) a second inductor arranged opposite the first inductor;
a first pair of external output terminals which are connected to the opposite ends, respectively, of the second inductor of said first mutual inductor pair, said first external output terminal pair outputting outside a voltage waveform induced by mutual inductance;
a second mutual inductor pair including a third inductor connected to an external variable power source and the fourth inductor arranged opposite the third inductor; and
a second pair of external output terminals which are connect to the opposite ends, respectively, of the fourth inductor of said second mutual inductor pair, said second pair of external output terminals outputting outside a voltage waveform induced by mutual inductance.
14. An integrated circuit as set forth in claim 13, further comprising:
a first switching unit which switches between connection and disconnection of the first inductor of said first mutual inductor pair to between the power source voltages; and
a second switching unit having the same construction as that of said first switching unit, said second switching unit switching between connection and disconnection of the third inductor of said second mutual inductor pair to said variable voltage source.
15. An integrated circuit as set forth in claim 13, wherein circuit patterns of the first inductor and the second inductor of said first mutual inductor pair is the same as those of the third inductor and the fourth inductor of said second mutual inductor pair.
16. An integrated circuit as set forth in claim 13, further comprising a first capacitor arranged between the power source voltages, said first capacitor being connected in series to the first inductor of said first mutual inductor pair; and
a second capacitor having the same construction as that of said first capacitor, said second capacitor being connected in series to the third inductor of said second mutual inductor pair.
17. An integrated circuit as set forth in claim 16, wherein circuit patterns of the first inductor, the first capacitor, and the second inductor of said first mutual inductor pair are the same as those of the third inductor, the second capacitor, and the fourth inductor, respectively, of said second mutual inductor pair.
18. An semiconductor device, comprising:
an integrated circuit having an internal circuit which is connected between power source voltages to operate with supply of the power source voltages, including:
a mutual inductor pair including (i) a first inductor connected between power source voltages and (ii) a second inductor placed opposite said first inductor; and
a pair of external output terminals which are connected to the opposite ends, respectively, of the second inductor of said mutual inductor pair, said external output terminal pair outputting outside a voltage waveform induced by mutual induction; and
a couple of external output terminals which are connected to said first pair of external output terminals, respectively, of said integrated circuit.
19. An semiconductor device, comprising:
an integrated circuit having an internal circuit which is connected between power source voltages to operate with supply of the power source voltages, including:
a first mutual inductor pair including (i) a first inductor connected between the power source voltages and (ii) a second inductor arranged opposite the first inductor;
a first pair of external output terminals which are connected to the opposite ends, respectively, of the second inductor of said first mutual inductor pair, said first external output terminal pair outputting outside a voltage waveform induced by mutual inductance;
a second mutual inductor pair including a third inductor connected to an external variable power source and the fourth inductor arranged opposite the third inductor; and
a second pair of external output terminals which are connect to the opposite ends, respectively, of the fourth inductor of said second mutual inductor pair, said second pair of external output terminals outputting outside a voltage waveform induced by mutual inductance; and
a plurality of external output terminals which are connected to said first pair of external output terminals and said second pair of external output terminals, respectively, of said integrated circuit.