1. A zoom lens comprising of, in order from an object side to an image side, a first lens unit having a positive refractive power, a second lens unit having a negative refractive power, a third lens unit having a positive refractive power, and a rear group including one or more lens units, wherein the first lens unit consists of a negative lens and a positive lens, the lens units move at a time of zooming, the position of the first lens unit at the telephoto end is displaced toward the object side from its position at the wide angle end, the position of the third lens unit at the telephoto end is displaced toward the object side from its position at the wide angle end, and the zoom lens satisfies the following conditional expressions:
10.5<f1fw<30.0, and
0.010<|f2ft|<0.181,
where f1 is the focal length of the first lens unit, f2 is the focal length of the second lens unit, fw is the focal length of the whole system at the wide angle end, and ft is the focal length of the whole system at the telephoto end.
2. A zoom lens according to claim 1, wherein the zoom lens satisfies the following conditional expression:
0.20<|f2f3|<0.85,
where f3 is the focal length of the third lens unit.
3. A zoom lens according to claim 1, wherein the zoom lens satisfies the following conditional expression:
2.0<f3fw<10.0,
where f3 is the focal length of the third lens unit.
4. A zoom lens according to claim 1, wherein the zoom lens satisfies the following conditional expression:
0.1<Tdwft<1.5,
where Tdw is the overall length of the zoom lens at the wide angle end.
5. A zoom lens according to claim 1, wherein the zoom lens satisfies the following conditional expression:
0.1<\u03b22w\u03b22t<0.4,
where \u03b22w is the lateral magnification of the second lens unit at the wide angle end, \u03b22t is the lateral magnification of the second lens unit at the telephoto end.
6. A zoom lens according to claim 1, wherein the zoom lens satisfies the following conditional expression:
0.01<D1Gft<0.15,
where D1G is the thickness of the first lens unit along the optical axis.
7. A zoom lens according to claim 1, wherein the rear group consists, in order from the object side to the image side, of a fourth lens unit having a negative refractive power and a fifth lens unit having a positive refractive power.
8. A zoom lens according to claim 7, wherein the zoom lens satisfies the following conditional expression:
0.01<|f2f4|<0.6,
where f4 is the focal length of the fourth lens unit.
9. A zoom lens according to claim 1, wherein the rear group consists of a fourth lens unit having a positive refractive power.
10. A zoom lens according to claim 9, wherein the zoom lens satisfies the following conditional expression:
0.01<|f2f4|<0.6,
where f4 is the focal length of the fourth lens unit.
11. A zoom lens according to claim 1, wherein the zoom lens satisfies the following conditional expression:
0.1<f1pf1<1.0,
where f1p is the focal length of the positive lens in the first lens unit.
12. A zoom lens according to claim 1 further comprising an aperture stop that is provided on the object side of the third lens unit and moves along a locus different from loci of the lens units at a time of zooming, wherein the zoom lens satisfies the following conditional expression:
0.5<dswfw<10.0,
where dsw is the distance between the aperture stop and the third lens unit at the wide angle end.
13. A zoom lens according to claim 1, wherein the third lens unit comprises one negative lens and two positive lenses.
14. A zoom lens according to claim 1, wherein the third lens unit is shifted in a direction having a component perpendicular to the optical axis to thereby shift the imaging position of the zoom lens in a direction perpendicular to the optical axis.
15. A zoom lens according to claim 1, wherein the zoom lens forms an image on a solid state image pickup element.
16. An image pickup apparatus comprising a zoom lens according to claim 1 and a solid state image pickup element that receives an image formed by the zoom lens.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A solid state storage device comprising:
a printed circuit board assembly;
a memory arranged on the printed circuit board assembly;
a storage medium arranged on the printed circuit board assembly;
a processor arranged on the printed circuit board assembly, wherein the processor is coupled to the memory and to the storage medium via the printed circuit board assembly, and wherein the processor is configured to store data in the memory and the storage medium and to read data from the memory and the storage medium; and
a removable power pack comprising a plurality of capacitors serially arranged in a housing, wherein the plurality of capacitors is detachably connected to the printed circuit board assembly to supply backup power to the processor, the memory, and the storage medium when the removable power pack is mounted in the solid state storage device.
2. The solid state storage device according to claim 1, wherein the housing comprises a plurality of cavities defined therein, and wherein each of the plurality of capacitors is arranged in a respective one of the plurality of cavities.
3. The solid state storage device according to claim 2, wherein the removable power pack further comprises a mounting circuit board connected to each of the plurality of capacitors, wherein the plurality of capacitors are serially connected to one another via the mounting circuit board, and wherein the mounting circuit board comprises a plurality of connectors configured to detachably connect to the printed circuit board assembly.
4. The solid state storage device according to claim 3, wherein the plurality of connectors comprises a plurality of pogo pins.
5. The solid state storage device according to claim 3, wherein the plurality of connectors comprises a plurality of contact pads.
6. The solid state storage device according to claim 3, wherein the housing and the mounting circuit board at least partially enclose the plurality of capacitors.
7. The solid state storage device according to claim 1, wherein the housing is formed of plastic.
8. The solid state storage device according to claim 1, further comprising:
a frame base, wherein the printed circuit board assembly is attached to the frame base; and
a frame cover attached to the frame base,
wherein the frame base and the frame cover partially enclose the printed circuit board assembly, the memory, the storage medium, and the processor, and
wherein the frame base and the frame cover define an opening for mounting the removable power pack in the solid state storage device.
9. The solid state storage device according to claim 1, further comprising a monitor circuit configured to monitor a voltage at a positive plate of each of the plurality of capacitors.
10. The solid state storage device according to claim 9, wherein the monitor circuit comprises an analog-to-digital convertor configured to convert the voltage at the positive plate of each of the plurality of capacitors to a respective digital value, and wherein the monitor circuit is further configured to communicate the respective digital values to the processor.
11. The solid state storage device according to claim 10, wherein the monitor circuit further comprises a plurality of voltage dividers configured to standardize the voltage at the positive plate of respective ones of the plurality of capacitors, wherein the monitor circuit is configured to monitor the respective standardized voltages.
12. The solid state storage device according to claim 1, further comprising an active balance network configured to equalize the respective voltages across the plurality of capacitors, wherein the active balance network comprises:
a first plurality of resistors arranged in a first voltage divider circuit configured to equally divide the total voltage across the plurality of capacitors; and
a plurality of op amps configured as voltage followers,
wherein the output of each of the plurality of op amps is coupled to a respective terminal connecting two adjacent capacitors, and an input of each of the plurality of op amps is coupled to a respective terminal connecting two adjacent resistors in the first voltage divider circuit.
13. The solid state storage device according to claim 12, wherein the active balance network is further configured to bring the voltage at the positive plate of each of the plurality of capacitors to a respective cumulative percentage of the total capacity of the plurality of capacitors.
14. The solid state storage device according to claim 12, further comprising a passive balance network configured to equalize the respective voltages across the plurality of capacitors, wherein the passive balance network comprises:
a second plurality of resistors arranged in second voltage divider circuit configured to equally divide the total voltage across the plurality of capacitors,
wherein each of the second plurality of resistors is arranged in parallel with a respective one of the plurality of capacitors.
15. A solid state storage device comprising:
a printed circuit board assembly;
a memory arranged on the printed circuit board assembly;
a storage medium arranged on the printed circuit board assembly;
a processor arranged on the printed circuit board assembly, wherein the processor is coupled to the memory and to the storage medium via the printed circuit board assembly, and wherein the processor is configured to store data in the memory and the storage medium and to read data from the memory and the storage medium;
a plurality of capacitors serially arranged and connected to the printed circuit board assembly to supply backup power to the processor, the memory, and the storage medium; and
a monitor circuit configured to monitor a voltage at a positive plate of each of the plurality of capacitors.
16. The solid state storage device according to claim 15, wherein the monitor circuit comprises an analog-to-digital convertor configured to convert the voltage at the positive plate of each of the plurality of capacitors to a respective digital value, and wherein the monitor circuit is further configured to communicate the respective digital values to the processor.
17. The solid state storage device according to claim 16, wherein the monitor circuit further comprises a plurality of voltage dividers configured to standardize the voltage at the positive plate of respective ones of the plurality of capacitors, wherein the monitor circuit is configured to monitor the respective standardized voltages.
18. The solid state storage device according to claim 15, wherein the plurality of capacitors are serially arranged in a housing of a removable power pack, and wherein the plurality of capacitors are configured to be detachably connected to the printed circuit board when the removable power pack is mounted in the solid state storage device.
19. A solid state storage device comprising:
a printed circuit board assembly;
a memory arranged on the printed circuit board assembly;
a storage medium arranged on the printed circuit board assembly;
a processor arranged on the printed circuit board assembly, wherein the processor is coupled to the memory and to the storage medium via the printed circuit board assembly, and wherein the processor is configured to store data in the memory and the storage medium and to read data from the memory and the storage medium;
a plurality of capacitors serially arranged and connected to the printed circuit board assembly to supply backup power to the processor, the memory, and the storage medium; and
an active balance network configured to equalize the respective voltages across the plurality of capacitors, wherein the active balance network comprises:
a first plurality of resistors arranged in a first voltage divider circuit configured to equally divide the total voltage across the plurality of capacitors; and
a plurality of op amps configured as voltage followers,
wherein the output of each of the plurality of op amps is coupled to a respective terminal connecting two adjacent capacitors, and an input of each of the plurality of op amps is coupled to a respective terminal connecting two adjacent resistors in the first voltage divider circuit.
20. The solid state storage device according to claim 19, wherein the active balance network is further configured to bring the voltage at the positive plate of each of the plurality of capacitors to a respective cumulative percentage of the total capacity of the plurality of capacitors.
21. The solid state storage device according to claim 19, further comprising a passive balance network configured to equalize the respective voltages across the plurality of capacitors, wherein the passive balance network comprises:
a second plurality of resistors arranged in second voltage divider circuit configured to equally divide the total voltage across the plurality of capacitors,
wherein each of the second plurality of resistors is arranged in parallel with a respective one of the plurality of capacitors.
22. The solid state storage device according to claim 19, wherein the plurality of capacitors are serially arranged in a housing of a removable power pack, and wherein the plurality of capacitors are configured to be detachably connected to the printed circuit board when the removable power pack is mounted in the solid state storage device.