1. A light guide plate unit comprising:
a light guide plate having a light incidence section provided along at least one side face of the light guide plate; and
a plurality of light sources that cause light to enter the light guide plate through the light incidence section,
the light incidence section including:
a plurality of first light incidence planes arranged along the side face;
a plurality of light guide sections formed in such a manner as to protrude outward from spaces between the plurality of first light incidence planes on the side face, respectively; and
a plurality of second light incidence planes positioned as protruding surfaces of the plurality of light guide sections, respectively,
the plurality of light sources including:
a plurality of first light sources provided in such a manner as to face the plurality of first light incidence planes, respectively; and
a plurality of second light sources provided in such a manner as to face the plurality of second light incidence planes, respectively.
2. The light guide plate unit as set forth in claim 1, wherein each of the light guide sections has a columnar shape or a conical shape or includes (i) a columnar region extending out of the light guide plate from the side face and (ii) a region protruding further outward from the columnar region and having a shape that gets wider toward an outside.
3. The light guide plate unit as set forth in claim 1, wherein the light incidence section is provided along plural side faces of the light guide plate.
4. A surface light source device comprising a light guide plate unit as set forth in claim 1.
5. A display device comprising a surface light source device as set forth in claim 4.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for providing direct bonding of wires to silicon for microelectronics and microelectromechanical systems (MEMS), said method comprising:
preparing a rough pothole during one of the many deep etch steps already performed in microelectronics and MEMS fabrication;
roughening of the smooth silicon surface in and around said rough pothole; and
plastically deforming a ball-bond into said rough pothole, such that the interconnection will eliminate a costly metallization layer, and thereby lower fabrication expenses and enable further high temperature processing.
2. The method according to claim 1, wherein the metallization layer eliminated is a gold layer.
3. The method according to claim 1, wherein the metallization layer eliminated is an aluminum layer.
4. The method according to claim 1, wherein the method is part of semiconductor device fabrication.
5. The method according to claim 4, wherein said fabrication uses passivation layers.
6. The method according to claim 5, wherein the passivation layers are used as hard masks.
7. The method according to claim 5, wherein the passivation layers are used as electric isolation.
8. The method according to claim 1, wherein said pothole is a silicon Deep Reactive Ion Etching (DRIE) pothole.
9. A system for providing direct bonding of wires to silicon for microelectronics and microelectromechanical systems (MEMS), said system comprising:
means for preparing a rough pothole during one of the many deep etch steps already performed in microelectronics and MEMS fabrication;
means for roughening of the smooth silicon surface in and around said rough pothole; and
means for plastically deforming a ball-bond into said rough pothole, such that the interconnection will eliminate a costly metallization layer, and thereby lower fabrication expenses and enable further high temperature processing.
10. The system according to claim 9, wherein the metallization layer eliminated is a gold layer.
11. The method according to claim 1, wherein the metallization layer eliminated is an aluminum layer.
12. The system according to claim 9, wherein the system is part of semiconductor device fabrication.
13. The system according to claim 12, wherein said fabrication uses passivation layers.
14. The system according to claim 13, wherein the passivation layers are used as hard masks.
15. The system according to claim 13, wherein the passivation layers are used as electric isolation.
16. The system according to claim 9, wherein said pothole is a silicon Deep Reactive Ion Etching (DRIE) pothole.