1. A method comprising:
forming a high-kmetal gate stack by:
forming a high-k dielectric layer on a substrate;
forming a work function metal layer on the high-k dielectric layer;
forming a silicide on the work function metal layer; and
forming a polycrystalline silicon (poly Si) layer on the silicide.
2. The method according to claim 1, comprising forming the silicide by:
forming a reactive metal layer in situ on the work function metal layer;
forming an amorphous silicon (a-Si) layer in situ on the entire upper surface of the reactive metal layer; and
annealing concurrently with forming the poly Si layer.
3. The method according to claim 2, comprising forming the work function metal layer including titanium nitride (TiN).
4. The method according to claim 3, comprising forming the reactive metal layer to a thickness of 1 nanometer (nm) to 3 nm.
5. The method according to claim 4, comprising forming the reactive metal layer including titanium (Ti).
6. The method according to claim 5, comprising forming the reactive metal layer by physical vapor deposition (PVD) including flash evaporation.
7. The method according to claim 6, comprising forming the a-Si layer to a thickness of 5 nm to 10 nm.
8. The method according to claim 7, comprising forming the a-Si layer by PVD.
9. The method according to claim 8, further comprising surface cleaning the a-Si layer prior to forming the poly Si layer.
10. The method according to claim 9, comprising surface cleaning the a-Si layer using hydrogen fluoride (HF).
11. The method according to claim 10, comprising surface cleaning the a-Si layer using HF within no more than 8 hours after forming the a-Si layer.
12. The method according to claim 11, comprising forming the poly Si layer by low-pressure chemical vapor deposition (LPCVD) at a temperature greater than 550\xb0 C.
13. The method according to claim 12 comprising forming the poly Si layer to a thickness of 15 nm to 200 nm.
14. The method according to claim 2, further comprising:
forming a high-kmetal gate by patterning and etching the high-kmetal gate stack; and
forming sourcedrain regions on opposite sides of the high-kmetal gate.
15. A device comprising:
a substrate;
a gate electrode stack formed on the substrate, the gate electrode stack comprising:
a high-k dielectric layer formed on the substrate;
a work function metal layer formed on the high-k dielectric layer;
a silicide layer formed on the work function metal layer;
an amorphous silicon (a-Si) layer formed on the silicide layer and covering the entire upper surface of the silicide layer; and
a polycrystalline silicon (poly Si) layer formed on the a-Si layer; and
sourcedrain regions formed on opposite sides of the gate electrode stack.
16. The device according to claim 15, wherein the work function layer includes titanium nitride (TiN).
17. The device according to claim 16, wherein the silicide comprises titanium silicide (TiSi).
18. The device according to claim 17, wherein the silicide has a thickness of 0.5 nm to 3 nm.
19. The device according to claim 18, wherein the poly Si layer has a thickness of 15 nm to 210 nm.
20. A method comprising:
forming a high-kmetal gate stack by:
forming a high-k dielectric layer on a substrate;
forming a work function metal layer including TiN to a thickness of 0.5 nm to 10 nm on the high-k dielectric layer;
forming a reactive metal layer including Ti in situ by PVD including flash evaporation to a thickness of 1 nm to 3 nm on the work function metal layer;
forming an amorphous silicon (a-Si) layer in situ by PVD to a thickness of 5 nm to 10 nm on the entire upper surface of the reactive metal layer;
surface cleaning the a-Si layer using HF within no more than 8 hours after forming the a-Si layer; and
forming a polycrystalline silicon (poly Si) layer by LPCVD at a temperature greater than 550\xb0 C. to a thickness of 15 nm to 200 nm on the a-Si layer;
forming a high-kmetal gate by patterning and etching the high-kmetal gate stack; and
forming sourcedrain regions on opposite sides of the high-kmetal gate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A single chip having multiple different devices integrated thereon for a common purpose, the chip comprising:
a silicon substrate having a peripheral area, a mid-chip area, and a central area;
a plurality of field effect transistors formed in the peripheral area, each field effect transistor having a layer including a rare earth in at least one of a conductive channel, a gate insulator, or a gate stack;
a plurality of photonic devices including at least one of light emitting diodes and vertical cavity surface emitting lasers formed in the mid-chip area, each photonic device having a layer including a rare earth; and
a plurality of photo detectors formed in the central area.
2. A chip as claimed in claim 1 wherein the silicon substrate includes one of a semiconductor-on-insulator (SOI) silicon substrate or a substrate including signal andor ground planes with double buried insulator layers.
3. A chip as claimed in claim 1 wherein the plurality of field effect transistors include double gate field effect transistors.
4. A chip as claimed in claim 1 wherein the plurality of field effect transistors are incorporated into driver circuits.
5. A chip as claimed in claim 1 wherein the plurality of field effect transistors are incorporated into AD or DA circuits.
6. A chip as claimed in claim 1 wherein the plurality of field effect transistors have gate insulators including a single crystal rare earth oxide, a rare earth nitride, a rare earth phosphide, or combinations thereof.
7. A chip as claimed in claim 1 wherein the plurality of field effect transistors have gate stacks including a single crystal rare earth dielectric.
8. A chip as claimed in claim 1 wherein the common purpose of the chip is analysis and the chip further includes a liquid retaining wall surrounding the central area for receiving therein a liquid to be analyzed.
9. A chip as claimed in claim 1 wherein the plurality of photonics devices include PiN diodes.
10. A chip as claimed in claim 1 wherein the layer including a rare earth of the photonic devices includes one of a rare earth oxide (RE2O3) and a rare earth silicate (RE2SiO5).
11. A chip as claimed in claim 10 wherein the RE radical in (RE2O3) and in (RE2SiO5) includes (Gd0.9Er0.1).
12. A single chip having multiple different devices integrated thereon for a common purpose, the chip comprising:
a substrate;
a contact layer of single crystal semiconductor material positioned on the substrate, the contact layer including an area having a doped portion and an overlying differently doped portion;
a first insulating layer epitaxially deposited on the contact layer and including one of a single crystal rare earth oxide and a single crystal rare earth silicate;
a first single crystal layer of doped semiconductor material epitaxially deposited on the first insulating layer;
a second insulating layer epitaxially deposited on the first single crystal layer of doped semiconductor material and including one of a single crystal rare earth oxide and a single crystal rare earth silicate;
a second single crystal layer of doped semiconductor material epitaxially deposited on the second insulating layer;
the second single crystal layer of doped semiconductor material in conjunction with the second insulating layer and the first single crystal layer of doped semiconductor material defining at least one field effect transistor, the first layer of semiconductor material, the first insulating layer, and the contact layer defining at least one photonics device, and the doped portion and the overlying differently doped portion of the contact layer defining at least one photodetector.
13. A chip as claimed in claim 12 wherein the one of single crystal rare earth oxide and the single crystal rare earth silicate included in the first and second insulating layers include (RE2O3) and (RE2SiO5), respectively.
14. A chip as claimed in claim 13 wherein the RE radical in (RE2O3) and in (RE2SiO5) includes (Gd0.9Er0.1).
15. A chip as claimed in claim 12 wherein the first single crystal layer of doped semiconductor material includes one of silicon and germanium.