1. A method of determining the earth ground resistance of at least one selected pylon footing comprising the steps of:
connecting a testing device to a voltage generation means and to an alternating current measurement device,
wherein, for each selected pylon footing:
the voltage generation means and current measurement device are placed around the footing;
a voltage is generated in the pylon footing using the voltage generation means;
the current induced by said voltage along the pylon footing using the current measurement device is measured; and
an earth resistance value is calculated for the footing, based on said voltage and measured current values.
2. The method of claim 1 comprising calculating the overall grounding resistance of a pylon based on the resistances of all parallel connected pylon footings.
3. The method of claim 1, wherein determining the earth ground resistance comprises for each selected pylon footing:
determining the complex components of the voltage and current; and
calculating a complex grounding impedance value of the footing.
4. The method of claim 3, wherein the complex grounding impedance is characterized using at least one of polar form with magnitude and phase and Cartesian form with real and imaginary parts.
5. The method of claim 3 comprising calculating the overall complex grounding impedance of a pylon based on the complex grounding impedances of all parallel connected pylon footings.
6. The method of claim 1 comprising repeating the aforementioned steps for a plurality of pylons.
7. The method of claim 1, wherein said current measurement device comprises a clamp.
8. The method of claim 7, wherein said clamp comprises at least one of a standard clamp, a flex clamp, a current transformer clamp, a fluxgate clamp, and a Hall effect clamp.
9. The method of claim 1, wherein said testing device comprises data storage means operative to store measurement data.
10. The method of claim 1, wherein said testing device includes a main unit and a remote unit adapted to communicate with one another.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. In a digital system comprising a processor, a device, and a bridge coupling the processor and the device, a method for the processor to perform a task of accessing the device via the bridge, the method comprising:
providing a processing circuit in the bridge;
building at least a first readwrite control block (RWCB) with the processors,
wherein building at least the first RWCB with the processor comprises building the first RWCB in a main memory coupled to the bridge and the processor;
signaling the processing circuit and switching to another task with the processor;
processing at least the first RWCB with the processing circuit to access the device; and
interrupting the processor with the processing circuit,
2. The method of claim 1, wherein providing the processing circuit in the bridge comprises providing a control block address register in the processing circuit for storing an address of the first RWCB.
3. The method of claim 2, wherein providing the processing circuit in the bridge further comprises providing a control block register in the processing circuit for storing the first RWCB.
4. The method of claim 3, wherein providing the processing circuit in the bridge further comprises providing an error status register in the processing circuit for storing a result of the processing of at least the first RWCB.
5. The method of claim 1, wherein building at least the first RWCB with the processor further comprises building a status field in the first RWCB for storing a result of the processing of the first RWCB.
6. The method of claim 5, wherein building at least the first RWCB with the processor further comprises building at least an addressdata field in the first RWCB for storing control data determining whether and how a read phase or a write phase corresponding to the addressdata field is to be performed.
7. The method of claim 6, wherein building at least the first RWCB with the processor further comprises building a link pointer field in the first RWCB for storing an address of a second RWCB.
8. The method of claim 5, wherein processing at least the first RWCB with the processing circuit to access the device comprises updating the status field in the first RWCB to reflect the result of the processing of the first RWCB.
9. The method of claim 1, further comprising obtaining, with the processor, a result of the processing of at least the first RWCB.
10. The method of claim 1, wherein the processing circuit is hardwired.
11. The method of claim 1, wherein the processing circuit is an application-specific integrated circuit.
12. A digital system, comprising a processor, a device, and a bridge coupling the processor and the device, wherein:
the bridge includes a processing circuit;
the processor is configured to:
build at least a first if readwrite control block (RWCB) in a main memory coupled to the bridge and the processor;
signal the processing circuit to access the device; and
switch to a task other than stalling waiting for a result of the accessing of the device by the processing circuit; and
the processing circuit is configured to process at least the first RWCB to access the device and interrupt the processor.
13. The system of claim 12, wherein the processing circuit comprises a control block address register configured to store an address of the first RWCB.
14. The system of claim 13, wherein the processing circuit further comprises a control block register configured to store the first RWCB.
15. The system of claim 14, wherein the processing circuit further comprises an error status register configured to store a result of the processing of at least the first RWCB.
16. The system of claim 12, wherein the processor is further configured to build a status field in the first RWCB for storing a result of the processing of the first RWCB.
17. The system of claim 16, wherein the processor is further configured to build at least an addressdata field in the first RWCB for storing control data determining whether and how a read phase or a write phase corresponding to the addressdata field is to be performed.
18. The system of claim 17, wherein the processor is further configured to build a link pointer field in the first RWCB for storing an address of a second RWCB.
19. The system of claim 16, wherein the processing circuit is further configured to update the status field in the first RWCB to reflect the result of the processing of the first RWCB.
20. The system of claim 12, wherein the processor is further configured to obtain a result of the processing of at least the first RWCB.
21. The system of claim 12, wherein the processing circuit is hardwired.
22. The system of claim 12, wherein the processing circuit is an application-specific integrated circuit.
23. In a digital system comprising a processor, a device, and a bridge coupling the processor and the device, the bridge including a processing circuit, a method for the processor to perform a task of accessing the device via the bridge, the method comprising;
building M readwrite control blocks (M RWCBs) with the processor, M being a positive integer;
signaling the processing circuit and switching to another task with the processor;
processing the M RWCBs with the processing circuit to access the device; and
interrupting the processor with the processing circuit;
wherein building the M RWCBs with the processor comprises, for each of the M RWCBs;
building at least one and at most N addressdata fields in the RWCB, each of the addressdata fields being for storing control data determining whether and how a read phase or a write phase corresponding to the addressdata field is to be performed, N being related to a size of the RWCB; and
building a link pointer field in the RWCB for storing an address of a next RWCB to form a chain of the M RWCBs to be processing circuit.