1. A double-stranded siRNA molecule comprising an antisense strand and a sense strand complementary to the antisense strand, wherein the siRNA molecule has at least one single nucleotide bulge having a gap without base-pairing formed by introducing a single nucleotide into the antisense strand, wherein the single nucleotide bulge is present at a second, eighteenth or nineteenth position from the 5\u2032 end region of antisense strand.
2. The double-stranded siRNA molecule of claim 1, wherein the single nucleotide bulge is present at a second position from the 5\u2032 end region of the antisense strand of the siRNA.
3. The double-stranded siRNA molecule of claim 1, wherein the introduced nucleotide is a nucleotide having a base different from that of a nucleotide which is adjacent thereto or an abasic nucleotide.
4. The double-stranded siRNA molecule of claim 1, wherein the siRNA molecule comprises a 19-21-nucleotide (nt) antisense strand and a 13-17-nt sense strand having a sequence complementary to the antisense strand, wherein the 5\u2032 end of the antisense strand is a blunt end, and the 3\u2032 end of the antisense strand has an overhang.
5. The double-stranded siRNA molecule of claim 4, wherein the length of the sense strand in the siRNA molecule is 15-16 nt, and the length of the overhang is 3-6 nt.
6. The double-stranded siRNA molecule of claim 1, wherein the siRNA molecule comprises a chemical modification.
7. The double-stranded siRNA molecule of claim 6, wherein the chemical modification is the substitution of the hydroxyl group at position 2\u2032 of the ribose of at least one nucleotide included in the siRNA by any one of a hydrogen atom, a fluorine atom, an -O-alkyl group, an -O-acyl group and an amino group.
8. The double-stranded siRNA molecule of claim 6, wherein the chemical modification is the substitution of the phosphate backbone of at least one nucleotide included in the siRNA by any one of a phosphorothioate form, a phosphorodithioate form, an alkylphosphonate form, a phosphoroamidate form and a boranophosphate form.
9. The double-stranded siRNA molecule of claim 6, wherein the chemical modification is the substitution of at least one nucleotide included in the siRNA by any one of LNA (locked nucleic acid), UNA (unlocked nucleic acid), morpholino, and PNA (peptide nucleic acid).
10. A gene silencing composition containing the siRNA molecule of claim 1.
11. A gene silencing kit containing the siRNA molecule of claim 1.
12. A method for silencing a target gene in a cell, the method comprising a step of introducing the siRNA molecule of claim 1 into the cell.
13. A method for silencing a target gene in a cell, the method comprising a step of expressing the siRNA molecule of claim 1 into the cell.
14. A method for suppressing off-target effects caused by the antisense strand of siRNA molecules, the method comprising a step of introducing the siRNA molecule of claim 1 into a cell.
15. A method for suppressing off-target effects caused by the antisense strand of siRNA molecules, the method comprising a step of expressing the siRNA molecule of claim 1 into a cell.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system comprising:
a plurality of physical processors;
one or more task queues;
a virtual machine manager configured to (a) request a first of the physical processors to execute a high priority virtual processor and to (b) wake at least a second of the physical processors to watch the one or more task queues for virtual processors that are preempted and queued in response to interrupting the first of the physical processors based at least on the request;
the first of the physical processors being configured to preempt a previously executing virtual processor in response to the request and to place the preempted virtual processor in the one or more task queues;
the second of the physical processors being configured upon being awakened to actively monitor the one or more task queues and to execute the preempted virtual processor; and
wherein the virtual machine manager is configured to wake the second processor without waiting for the first processor to place the preempted virtual processor in the one or more queues.
2. The system of claim 1, wherein the virtual machine manager requests the first of the physical processors to execute the high priority virtual processor by generating an inter-processor interrupt for interrupting the first of the physical processors.
3. The system of claim 1, wherein the virtual machine manager wakes the second of the physical processors by generating an inter-processor interrupt.
4. The system of claim 1, wherein the second of the physical processors is configured to actively monitor the one or more task queues for a predetermined time.
5. The system of claim 1, wherein the second of the physical processors is configured to watch the one or more task queues for a time that is based at least in part on the priority of the preempted virtual processor.
6. The system of claim 1, wherein the second of the physical processors is configured to watch the one or more task queues for a time that is based at least in part on an expected time for the first of the physical processors to place the preempted virtual processor in the one or more task queues.
7. The system of claim 1, wherein the second of the physical processors is configured to watch the one or more task queues for a time that is based at least in part on an observed time for the first of the physical processors to place the preempted virtual processor in the one or more task queues.
8. The system of claim 1, wherein the high priority virtual processor is not compatible with being executed by the second of the physical processors.
9. The system of claim 1, wherein the preempted virtual processor is compatible with being executed by at least one of the plurality of physical processors.
10. The system of claim 1, wherein the first of the physical processors is configured to (a) preempt a low-priority virtual processor in response to the request; (b) place the preempted low-priority virtual processor in the one or more task queues, and (c) not wake the second of the physical processors upon placing the preempted low-priority virtual processor in the one or more task queues.
11. The system of claim 1, wherein the virtual machine concurrently wakes multiple physical processors that are predicted to execute preempted tasks in response to preempting the previously executing virtual processor.
12. A computer-implemented method, comprising:
under control of one or more processors configured with executable instructions,
executing a first task on a first processor;
interrupting the first processor to execute a second task on the first processor;
interrupting a second processor to monitor tasks in a task queue in response to the interrupting of the first processor, wherein interrupting the second processor comprises waking the second processor without waiting for the first task to be placed in the task queue;
preempting the first task and placing the first task in the task queue in response to interrupting the first processor; and
resuming the first task on the second processor after the first task is placed in the task queue.
13. The method of claim 12, wherein the interrupting is performed by an operating system scheduler.
14. The method of claim 12, wherein the interrupting is performed by a virtual machine scheduler.
15. The method of claim 12, further comprising interrupting a plurality of processors to monitor tasks in the task queue concurrently with interrupting the first processor to execute the second task, wherein the plurality of processors comprise processors that are predicted to execute preempted tasks in response to interrupting the first processor.
16. The method of claim 12, wherein the first and second processors comprise virtual processors.
17. The method of claim 12, wherein the first and second tasks comprise virtual processors.
18. The method of claim 12, wherein the first and second processors comprise physical processors.
19. The method of claim 12, wherein the first and second tasks comprise execution threads.
20. The method of claim 12, wherein interrupting the first processor comprises generating an inter-processor interrupt to the first processor.
21. The method of claim 12, wherein waking the second processor comprises generating an inter-processor interrupt to the second processor.
22. The method of claim 12, wherein the second processor is configured to actively monitor the task queue for a predetermined time in response to waking the second processor.
23. The method of claim 12, wherein the second processor is configured to actively monitor the task queue for a time that is based at least in part on the priority of the first task.
24. The method of claim 12, wherein the second processor is configured to actively monitor the task queue for a time that is based at least in part on an expected time for the first processor to place the first task in the task queue.
25. The method of claim 12, wherein the second processor is configured to actively monitor the task queue for a time that is based at least in part on an observed time for the first processor to place the first task in the task queue.
26. The method of claim 12, wherein the first processor is configured to not wake the second processor when placing the first task in the task queue.
27. The method of claim 12, further comprising interrupting a plurality of processors to watch for tasks in the task queue concurrently with interrupting the first processor to execute the second task, wherein the plurality of processors comprise processors that are predicted to execute preempted tasks in response to interrupting the first processor.
28. One or more non-transitory computer-readable media containing instructions that are executable by one or more processors to perform actions comprising:
executing a first task on a first processor;
interrupting the first processor to execute a second task;
interrupting a second processor to watch for tasks in a task queue in response to the interrupting of the first processor, wherein interrupting the second processor is performed without waiting for the first processor to respond to interrupting the first processor and without waiting for the first task to be placed in the task queue;
in response to interrupting the first processor, preempting the first task on the first processor and placing the first task in the task queue; and
resuming the first task on the second processor after the first task is placed in the task queue.
29. The one or more non-transitory computer-readable media of claim 28, the acts further comprising interrupting a plurality of processors to watch for tasks in the task queue, without waiting for the first processor to respond to interrupting the first processor, wherein the plurality of processors comprise processors that are predicted to execute preempted tasks in response to interrupting the first processor.
30. The one or more non-transitory computer-readable media of claim 28, wherein interrupting the first processor comprises generating an inter-processor interrupt to the first processor.
31. The one or more non-transitory computer-readable media of claim 28, wherein interrupting the second processor comprises generating an inter-processor interrupt to the second processor.
32. The one or more non-transitory computer-readable media of claim 28, wherein the second processor is configured to actively monitor the task queue for a predetermined time in response to interrupting the second processor.
33. The one or more non-transitory computer-readable media of claim 28, wherein the second processor is configured to actively monitor the task queue for a time that is based at least in part on the priority of the first task.
34. The one or more non-transitory computer-readable media of claim 28, wherein the second processor is configured to actively monitor the task queue for a time that is based at least in part on an expected time for the first processor to place the first task in the task queue.
35. The one or more non-transitory computer-readable media of claim 28, wherein the second processor is configured to actively monitor the task queue for a time that is based at least in part on an observed time for the first processor to place the first task in the task queue.
36. The one or more non-transitory computer-readable media of claim 28, wherein the first processor is configured to not interrupt the second processor when placing the first task in the task queue.