1. A method for testing an array of configuration random-access memory elements on a programmable logic device for the presence of resistive bridging faults at their outputs, comprising:
writing test configuration data into the configuration random-access memory elements;
clearing programmable logic registers on the programmable logic device;
sensitizing the array to resistive bridging faults by performing read operations on the configuration random-access memory elements; and
applying test vectors to the programmable logic registers and observing corresponding test results to determine whether any of the sensitized configuration random-access memory elements have associated resistive bridging faults.
2. The method defined in claim 1 wherein applying the test vectors comprises checking the array for proper operation immediately after sensitizing the array without performing any intervening error correction code error detection operations on the test configuration data.
3. The method defined in claim 1 wherein applying the test vectors comprises checking the array for proper operation immediately after sensitizing the array without performing any intervening cyclic redundancy check error detection operations on the test configuration data.
4. The method defined in claim 1 wherein the array has an associated data register and wherein applying the test vectors comprises checking the array for proper operation immediately after sensitizing the array without performing any intervening data shifting operations using the data register.
5. The method defined in claim 1 wherein the programmable logic device has input-output pins, wherein applying the test vectors comprises checking the array for proper operation using direct observation immediately after sensitizing the array without performing any intervening error correction code error detection operations on the test configuration data, and wherein using direct observation comprises:
with a tester, applying at least part of the test vectors to at least some of the input-output pins while observing the test results on at least some of the input-output pins.
6. The method defined in claim 1 wherein applying the test vectors comprises checking the array for proper operation using scan chain testing immediately after sensitizing the array without performing any intervening error correction code error detection operations on the test configuration data.
7. The method defined in claim 1, wherein applying the test vectors comprises checking the array for proper operation using scan chain testing immediately after sensitizing the array without performing any intervening error correction code error detection operations on the test configuration data and wherein using scan chain testing comprises:
with a tester, applying at least part of the test vectors using a scan chain formed from at least some of the programmable logic registers.
8. The method defined in claim 1 wherein applying the test vectors comprises checking the array for proper operation using scan chain testing immediately after sensitizing the array without performing any intervening error correction code error detection operations on the test configuration data and wherein using scan chain testing comprises:
with a tester, observing at least part of the test results using a scan chain formed from at least some of the programmable logic registers.
9. The method defined in claim 1 wherein the array comprises data lines and wherein sensitizing the array comprises precharging the data lines.
10. The method defined in claim 1 wherein the array comprises data lines and precharge drivers that drive the data lines and wherein sensitizing the array comprises:
precharging the data lines with the precharge drivers; and
tristating the precharge drivers after precharging the data lines.
11. The method defined in claim 1 wherein the array comprises data lines, precharge drivers that drive the data lines, and address lines and wherein sensitizing the array comprises:
precharging the data lines with the precharge drivers;
tristating the precharge drivers after precharging the data lines; and
systematically asserting the address lines to read from the array after tristating the precharge drivers.
12. The method defined in claim 1 wherein the programmable logic comprises metal-oxide-semiconductor transistors having gates and wherein the configuration random-access memory elements each include:
an address transistor;
a clear transistor;
an output line that is coupled to the gate of a respective one of the programmable logic metal-oxide-semiconductor transistors; and
a pair of cross-coupled inverters having an inverted data node that is connected to the address transistor and a data node that is connected to the clear transistor and the output line, wherein applying test vectors to the programmable logic registers comprises applying test vectors to the programmable logic registers to determine whether unwanted resistive paths are present that bridge the gates of any of the metal-oxide-semiconductor transistors.
13. A method for testing an array of configuration random-access memory elements on a programmable logic device for the presence of resistive bridging faults at their outputs, wherein the programmable logic device comprises programmable logic that includes metal-oxide-semiconductor transistors having gates and that includes programmable logic registers, and wherein the configuration random-access memory elements each include an address transistor, a clear transistor, an output line that is coupled to the gate of a respective one of the programmable logic metal-oxide-semiconductor transistors, and a pair of cross-coupled inverters having an inverted data node that is connected to the address transistor and a data node that is connected to the clear transistor and the output line, the method comprising the steps of:
sensitizing the array to resistive bridging faults by performing read operations on the configuration random-access memory elements; and
applying test vectors to the programmable logic registers and observing corresponding test results to determine whether any one of the sensitized configuration random-access memory elements has an associated resistive bridging fault that bridges the gate of the metal-oxide-semiconductor transistor that is coupled to its output line.
14. The method defined in claim 13 further comprising:
before sensitizing the array, writing test configuration data into the configuration random-access memory elements and clearing the programmable logic registers on the programmable logic device.
15. The method defined in claim 13 further comprising:
before sensitizing the array, placing the programmable logic device in user mode to clear the programmable logic registers on the programmable logic device, wherein applying the test vectors to the programmable logic registers and observing corresponding test results to determine whether any one of the sensitized configuration random-access memory elements has an associated resistive bridging fault comprises applying the test vectors to the programmable logic registers and observing corresponding test results to determine whether any one of the sensitized configuration random-access memory elements has an associated resistive bridging fault that can only be detected in the user mode.
16. The method defined in claim 13 wherein applying test vectors to the programmable logic registers and observing corresponding test results comprises applying test vectors to the programmable logic registers and observing corresponding test results immediately after sensitizing the array without performing any intervening error correction code error detection operations.
17. The method defined in claim 13 wherein applying test vectors to the programmable logic registers and observing corresponding test results comprises checking whether the metal-oxide-semiconductor transistors have been turned on and off as expected by the configuration random-access memory elements.
18. The method defined in claim 13 wherein applying test vectors to the programmable logic registers and observing corresponding test results comprises using scan chain testing to check whether the metal-oxide-semiconductor transistors have been turned on and off as expected by the configuration random-access memory elements.
19. The method defined in claim 13 wherein applying test vectors to the programmable logic registers and observing corresponding test results comprises using direct observation testing in which test signals are applied and test results are observed through input-output pins to check whether the metal-oxide-semiconductor transistors have been turned on and off as expected by the configuration random-access memory elements.
20. The method defined in claim 13 wherein the array comprises data lines, precharge drivers that drive the data lines, and address lines, wherein the data lines are connected to the address transistors, wherein the address transistors each have an address transistor gate, wherein the address lines are each connected to a respective one of the address transistor gates, and wherein sensitizing the array comprises:
precharging the data lines with the precharge drivers;
tristating the precharge drivers; and
systematically asserting the address lines to read from the array.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
associating at least one historical event with at least one media content event based, at least in part, upon a chronological relationship;
displaying a chronological representation of the at least one historical event and the at least one media content event within a window of time;
receiving a user selection of an informational item displayed within the chronological representation; and
updating the chronological representation based on the selected informational item.
2. The method of claim 1 wherein the informational item is chosen from the group consisting of: the at least one historical event; the at least one media content event; a window of time; and media metadata.
3. The method of claim 2 wherein the media metadata is chosen from the group consisting of: an artist identifier, an album identifier, a track identifier, and a music genre identifier.
4. The method of claim 1 further comprising:
in response to receiving a user selection of an informational item, identifying one or more media content events and one or more historical events having an associated date corresponding to the selected informational item.
5. The method of claim 1 wherein updating the chronological representation includes narrowing a chronological scope of the chronological representation.
6. The method of claim 1 wherein updating the chronological representation includes filtering the chronological representation based upon the selected informational item.
7. A computer program product residing on a computer readable medium having a plurality of instructions stored thereon that, when executed by a processor, cause the processor to perform operations comprising:
associating at least one historical event with at least one media content event based, at least in part, upon a chronological relationship;
displaying a chronological representation of the at least one historical event and the at least one media content event within a window of time;
receiving a user selection of an informational item displayed within the chronological representation; and
updating the chronological representation based on the selected informational item.
8. The computer program product of claim 7 wherein the informational item is chosen from the group consisting of: the at least one historical event; the at least one media content event; a window of time; and media metadata.
9. The computer program product of claim 8 wherein the media metadata is chosen from the group consisting of: an artist identifier, an album identifier, a track identifier, and a music genre identifier.
10. The computer program product of claim 7 further comprising instructions for performing operations comprising:
in response to receiving a user selection of an informational item, identifying one or more media content events and one or more historical events having an associated date corresponding to the selected informational item.
11. The computer program product of claim 7 wherein the instructions for updating the chronological representation include instructions for narrowing a chronological scope of the chronological representation.
12. The computer program product of claim 7 wherein the instructions for updating the chronological representation include instructions for filtering the chronological representation based upon the selected informational item.
13. A computing device configured to perform operations comprising:
associating at least one historical event with at least one media content event based, at least in part, upon a chronological relationship;
displaying a chronological representation of the at least one historical event and the at least one media content event within a window of time;
receiving a user selection of an informational item displayed within the chronological representation; and
updating the chronological representation based on the selected informational item.
14. The computing device of claim 13 wherein the informational item is chosen from the group consisting of: the at least one historical event; the at least one media content event; a window of time; and media metadata.
15. The computing device of claim 14 wherein the media metadata is chosen from the group consisting of: an artist identifier, an album identifier, a track identifier, and a music genre identifier.
16. The computing device of claim 13, wherein the computing device is further configured to perform operations comprising:
in response to receiving a user selection of an informational item, identifying one or more media content events and one or more historical events having an associated date corresponding to the selected informational item.
17. The computing device of claim 13 wherein updating the chronological representation includes narrowing a chronological scope of the chronological representation.
18. The computing device of claim 13 wherein updating the chronological representation includes filtering the chronological representation based upon the selected informational item.
19. The computing device of claim 13 wherein the computing device is chosen from the group consisting of a personal media device, a client computer, a personal digital assistant, a cellular telephone, a television, a cable box, an internet radio, and a dedicated network device.