1. A method for fabricating a fuse of a semiconductor device, the method comprising:
forming a barrier metal layer and a metal layer over a first insulating film;
patterning the metal layer and the barrier metal layer to form a fuse pattern;
etching sidewalls of the patterned barrier metal layer to form an undercut;
forming a protective film that fills the undercut;
forming a second insulating film over the protective film, the fuse pattern and the barrier metal; and
selectively etching the first insulating film and the second insulating film to form a fuse open region.
2. The method according to claim 1, wherein the first insulating film and the second insulating film comprise oxide films.
3. The method according to claim 1, wherein the protective film comprises an oxide film.
4. The method according to claim 1, wherein the barrier metal layer comprises one selected from the group consisting of a titanium (Ti) film and a titanium nitride (TiN) film.
5. The method according to claim 1, wherein the metal layer comprises aluminum.
6. The method according to claim 1, wherein the width of the undercut ranges from about 40 \u212b to about 60 \u212b.
7. The method according to claim 1, wherein the forming-a-protective-film comprises forming a protective film over the fuse pattern including the first insulating film and the undercut.
8. The method according to claim 1, wherein the forming-a-fuse-open-region comprises etching the protective film with the fuse pattern as a barrier so that the protective film remains on the undercut.
9. The method according to claim 1, wherein a passivation layer is further comprised over the second insulating film.
10. The method according to claim 9, wherein the passivation layer comprises one selected from the group consisting of an oxide film and a nitride film.
11. The method according to claim 1, further comprising etching the upper portion of the fuse pattern.
12. A fuse of a semiconductor device comprising:
a fuse pattern including an undercut; and
a protective film filled in the undercut.
13. The fuse according to claim 12, wherein the fuse pattern comprises a metal layer and a barrier metal layer.
14. The fuse according to claim 13, wherein the metal layer comprises aluminum.
15. The fuse according to claim 13, wherein the barrier metal layer comprises one selected from the group consisting of a titanium (Ti) film and a titanium nitride (TiN) film.
16. The fuse according to claim 12, wherein the width of the undercut ranges from about 40 \u212b to about 60 \u212b.
17. The fuse according to claim 13, wherein the undercut is formed in the barrier metal layer.
18. The fuse according to claim 12, wherein the protective film comprises an oxide film.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for manufacturing a semiconductor device comprising the steps of:
performing a first ion implanting process for implanting an n-type impurity with a first dose on a surface of a semiconductor wafer to form an n-type impurity layer on the surface of the semiconductor wafer;
coating resist on the surface of the side where the n-type impurity layer is formed in the semiconductor wafer;
exposing the semiconductor wafer selectively to pattern the resist; and
performing a second ion implanting process for implanting a p-type impurity with a second dose greater than the first dose using the remaining part of the resist as a mask to form a p-type impurity layer in the interior of the n-type impurity layer.
2. The method for manufacturing the semiconductor device according to claim 1, wherein the second ion implanting process is split into two or more times and is performed until the dose of the p-type impurity reaches the second dose, and wherein each dose of the ion implanting processes split into two or more times is less than the second dose.
3. The method for manufacturing the semiconductor device according to claim 1, wherein Rp1, \u0394Rp1, Rp2, and \u0394Rp2 are defined as the projected range of the n-type impurity in the first ion implanting process, the standard deviation of the projected range Rp1, the projected range of the p-type impurity in the second ion implanting process, and the standard deviation of the projected range Rp2, respectively, and wherein the following equation 1 is satisfied as:
Rp2+3\xb7\u0394Rp2\u2267Rp1+3\u0394Rp1 \u2003\u2003(1)
4. The method for manufacturing the semiconductor device according to claim 1, wherein the method further includes heat treatment to activate the n-type impurity layer and the p-type impurity layer after the second ion implanting process, and wherein N1, N2, xj1, and xj2 are defined as the first dose, the second dose, the diffusion depth of the n-type impurity layer after heat treatment, and the diffusion depth of p-type impurity layer after heat treatment, respectively, wherein the following equation 2 is satisfied as:
N2>N1\xb7(xj2xj1) \u2003\u2003(2)
5. The method for manufacturing the semiconductor device according to claim 1, wherein the second dose of the p-type impurity layer is equal to or greater than 1.0\xd71015 cm\u22122.
6. The method for manufacturing the semiconductor device according to claim 1, wherein the method further includes a thinning process grinding a principal surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer before the first ion implanting process, wherein the thinning process allows the thickness of the semiconductor wafer to be reduced to 200 \u03bcm or less, and wherein the first ion implanting process implants the n-type impurity on the surface of the semiconductor wafer which has been ground.
7. The method for manufacturing the semiconductor device according to claim 2, wherein Rp1, \u0394Rp1, Rp2, and \u0394Rp2 are defined as the projected range of the n-type impurity in the first ion implanting process, the standard deviation of the projected range Rp1, the projected range of the p-type impurity in the second ion implanting process, and the standard deviation of the projected range Rp2, respectively, and wherein the following equation 1 is satisfied as:
Rp2+3\xb7\u0394Rp2\u2267Rp1+3\u0394Rp1 \u2003\u2003(1)
8. The method for manufacturing the semiconductor device according to claim 2, wherein the method further includes heat treatment to activate the n-type impurity layer and the p-type impurity layer after the second ion implanting process, and wherein N1, N2, xj1, and xj2 are defined as the first dose, the second dose, the diffusion depth of the n-type impurity layer after heat treatment, and the diffusion depth of p-type impurity layer after heat treatment, respectively, wherein the following equation 2 is satisfied as:
N2>N1\xb7(xj2xj1) \u2003\u2003(2)
9. The method for manufacturing the semiconductor device according to claim 3, wherein the method further includes heat treatment to activate the n-type impurity layer and the p-type impurity layer after the second ion implanting process, and wherein N1, N2, xj1, and xj2 are defined as the first dose, the second dose, the diffusion depth of the n-type impurity layer after heat treatment, and the diffusion depth of p-type impurity layer after heat treatment, respectively, wherein the following equation 2 is satisfied as:
N2>N1\xb7(xj2xj1) \u2003\u2003(2)
10. The method for manufacturing the semiconductor device according to claim 2, wherein the second dose of the p-type impurity layer is equal to or greater than 1.0\xd71015 cm\u22122.
11. The method for manufacturing the semiconductor device according to claim 3, wherein the second dose of the p-type impurity layer is equal to or greater than 1.0\xd71015 cm\u22122.
12. The method for manufacturing the semiconductor device according to claim 4, wherein the second dose of the p-type impurity layer is equal to or greater than 1.0\xd71015 cm\u22122.
13. The method for manufacturing the semiconductor device according to claim 2, wherein the method further includes a thinning process grinding a principal surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer before the first ion implanting process, wherein the thinning process allows the thickness of the semiconductor wafer to be reduced to 200 \u03bcm or less, and wherein the first ion implanting process implants the n-type impurity on the surface of the semiconductor wafer which has been ground.
14. The method for manufacturing the semiconductor device according to claim 3, wherein the method further includes a thinning process grinding a principal surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer before the first ion implanting process, wherein the thinning process allows the thickness of the semiconductor wafer to be reduced to 200 \u03bcm or less, and wherein the first ion implanting process implants the n-type impurity on the surface of the semiconductor wafer which has been ground.
15. The method for manufacturing the semiconductor device according to claim 4, wherein the method further includes a thinning process grinding a principal surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer before the first ion implanting process, wherein the thinning process allows the thickness of the semiconductor wafer to be reduced to 200 \u03bcm or less, and wherein the first ion implanting process implants the n-type impurity on the surface of the semiconductor wafer which has been ground.
16. The method for manufacturing the semiconductor device according to claim 5, wherein the method further includes a thinning process grinding a principal surface of the semiconductor wafer to reduce the thickness of the semiconductor wafer before the first ion implanting process, wherein the thinning process allows the thickness of the semiconductor wafer to be reduced to 200 \u03bcm or less, and wherein the first ion implanting process implants the n-type impurity on the surface of the semiconductor wafer which has been ground.