1-19. (canceled)
20. An optoelectronic semiconductor chip, comprising:
a semiconductor body that comprises an active region that generates electromagnetic radiation during operation;
a first mirror layer located to reflect the electromagnetic radiation;
a first encapsulation layer formed by an electrically insulating material; and
a carrier mechanically supporting the first encapsulation layer, the first mirror layer and the semiconductor body;
wherein the first mirror layer is arranged between the carrier and the semiconductor body;
wherein the first encapsulation layer is arranged between the carrier and the first mirror layer; and
wherein the first encapsulation layer is an ALD layer.
21. The optoelectronic semiconductor chip according to claim 20, further comprising a through-contact that passes through the first encapsulation layer, the first mirror layer and the active region.
22. The optoelectronic semiconductor chip according to claim 21, wherein, apart from any through-contacts, the semiconductor body is fully enclosed by encapsulation layers which are ALD layers.
23. The optoelectronic semiconductor chip according to claim 21, wherein the first encapsulation layer fully covers the carrier on an upper side facing toward the semiconductor body except for regions in which one or more through-contacts passes through the first encapsulation layer.
24. The optoelectronic semiconductor chip according to claim 21, further comprising a second mirror layer arranged on a lower side of the through-contact facing toward the carrier, wherein the first encapsulation layer is arranged in regions between the first mirror layer and the second mirror layer.
25. The optoelectronic semiconductor chip according to claim 21, wherein the carrier is electrically conductive and wherein the carrier is electrically conductively connected to the through-contact.
26. The optoelectronic semiconductor chip according to claim 20, further comprising a third mirror layer that extends beyond a side surface of the semiconductor body in a lateral direction, wherein the first encapsulation layer extends at least in regions on a side, facing away from the carrier, of the third mirror layer.
27. The optoelectronic semiconductor chip according to claim 20, wherein a side surface of the first mirror layer is free of the first encapsulation layer.
28. The optoelectronic semiconductor chip according to claim 20, wherein the first encapsulation layer has a thickness of between at least 0.05 nm and at most 500 nm.
29. The optoelectronic semiconductor chip according to claim 20, further comprising a second encapsulation layer arranged between the carrier and the first encapsulation layer, wherein the second encapsulation layer is electrically insulating, wherein the second encapsulation layer is in direct contact with the first encapsulation layer, and wherein the second encapsulation layer covers at least 90% of an outer surface of the first encapsulation layer.
30. The optoelectronic semiconductor chip according to claim 29, further comprising a third encapsulation layer arranged between the first encapsulation layer and the semiconductor body, wherein the third encapsulation layer is electrically insulating, wherein the third encapsulation layer is in direct contact with the first encapsulation layer, and wherein the third encapsulation layer covers at least 90% of an outer surface of the first encapsulation layer.
31. The optoelectronic semiconductor chip according to claim 30, wherein a thickness of the second encapsulation layer and of the third encapsulation layer is at least six times a thickness of the first encapsulation layer.
32. The optoelectronic semiconductor chip according to claim 30, further comprising a fourth encapsulation layer that fully covers regions of an outer surface of the semiconductor body that are not covered by the carrier and wherein the fourth encapsulation layer is an ALD layer.
33. The optoelectronic semiconductor chip according to claim 32, wherein the first encapsulation layer and the fourth encapsulation layer are in direct contact with one another in regions.
34. The optoelectronic semiconductor chip according to claim 32, further comprising a fifth encapsulation layer that is electrically insulating and is in direct contact with the fourth encapsulation layer.
35. The optoelectronic semiconductor chip according to claim 34, wherein at least one of the second, third or fifth encapsulation layers comprises at least two partial layers that are formed by a different material to one another.
36. The optoelectronic semiconductor chip according to claim 32, further comprising an electrical connection region arranged laterally separated from the semiconductor body, wherein the electrical connection region is laterally enclosed fully by the first encapsulation layer, the fourth encapsulation layer or a combination of the first and fourth encapsulation layers.
37. A method for producing an optoelectronic semiconductor chip according to claim 20, wherein the first encapsulation layer is produced by an ALD method, and wherein the first encapsulation layer is deposited at least in regions by using ozone as a precursor.
38. The method according to the claim 37, wherein the first encapsulation layer comprises a first sublayer that is deposited using a precursor that is free of ozone, wherein the first sublayer is deposited directly onto a mirror layer, wherein the first encapsulation layer comprises a second sublayer that deposited using a precursor that comprises ozone, and wherein the second sublayer is deposited directly onto the first sublayer.
39. An optoelectronic semiconductor chip, comprising:
a semiconductor body that comprises an active region that generates electromagnetic radiation during operation;
a first mirror layer located to reflect the electromagnetic radiation;
a first encapsulation layer formed by an electrically insulating material;
a through-contact; and
a carrier for mechanically supporting the first encapsulation layer, the first mirror layer and the semiconductor body;
wherein the first mirror layer is arranged between the carrier and the semiconductor body;
wherein the first encapsulation layer is arranged between the carrier and the first mirror layer;
wherein the first encapsulation layer is an ALD layer;
wherein the through-contact passes through the first encapsulation layer, the first mirror layer and the active region; and
wherein apart from the through-contact, the semiconductor body is fully enclosed by encapsulation layers which are ALD layers.
40. The optoelectronic semiconductor chip according to claim 39, further comprising an electrical connection region that is arranged laterally separated from the semiconductor body, wherein the electrical connection region is laterally enclosed fully by the first encapsulation layer, a fourth encapsulation layer, or a combination of the first and fourth encapsulation regions.
41. An optoelectronic semiconductor chip, comprising:
a semiconductor body, which comprises an active region that generates electromagnetic radiation during operation;
a first mirror layer located to reflect the electromagnetic radiation;
a first encapsulation layer formed by an electrically insulating material;
a third encapsulation layer arranged between the first encapsulation layer and the semiconductor body; and
a carrier for mechanically supporting the first encapsulation layer, the first mirror layer and the semiconductor body;
wherein the first mirror layer is arranged between the carrier and the semiconductor body;
wherein the first encapsulation layer is arranged between the carrier and the first mirror layer;
wherein the first encapsulation layer is an ALD layer;
wherein the third encapsulation layer is electrically insulating;
wherein the third encapsulation layer is in direct contact with the first encapsulation layer; and
wherein the third encapsulation layer covers at least 90% of an outer surface, facing toward it, of the first encapsulation layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device structure, the structure comprising:
an active region and an isolation region, disposed in proximity to each other on a substrate;
a plurality of gate structures each having a gate conductive layer, disposed on the substrate, wherein each of first portions of the gate structures, disposed on the active region, further comprise a cap layer and a spacer, and second portions of the gate structures, disposed on the isolation region, do not comprise a cap layer and a spacer;
a dielectric layer, disposed above the gate structures;
a self-aligned contact, disposed in the dielectric layer and between two of the first portions of the gate structures; and
a conductive line, disposed on the dielectric layer, wherein the conductive line electrically connects with the self-aligned contact,
wherein a dielectric constant of the dielectric layer is lower than a dielectric constant of the cap layer and the spacer.
2. The structure of claim 1, wherein the spacer of one of the two first portions of the gate structures is disposed between the self-aligned contact and the gate conductive layer of said one of the two first portions of the gate structures, and between the self-aligned contact and a remaining part of the cap layer of said one of the two first portions of the gate structures.
3. The structure of claim 1 further comprising a metal silicide layer formed on a sidewall of each of the gate conductive layers of the second portions of the gate structures.
4. The structure of claim 3, wherein the gate conductive layer of one of the first portions of the gate structures has a sidewall that is not adjacent to the self-aligned contact, and said sidewall further comprises a metal silicide layer.