1. A method comprising:
configuring a software application with multiple time axes to represent one or more time elements; and further
configuring the software application to present a user with a selection of one or more of the multiple time axes.
2. The method of claim 1, further comprising configuring the software application with a time zone code and a daylight savings time indicator, thereby providing the software application with an ability to differentiate a duplicate hour in transitioning between daylight savings time and standard time.
3. The method of claim 1, wherein
the one or more time axes include a time portion and a date portion; and
the multiple time axes comprise one or more of a twenty four hour day time axis, a Gregorian date axis, a UTC time axis, a local date and time axis offset from the UTC time axis, a local date and time axis including time zone data and a daylight savings time indicator, and a date and time axis independent of a time zone.
4. The method of claim 3, wherein one or more of the multiple time axes further comprises a timepoint to indicate a dimensionless point in time.
5. The method of claim 1, wherein the configuration of the software application permits an exchange of time information via a specification of the one or more multiple time axes.
6. The method of claim 1, further comprising:
configuring the software application so as to enable a user at run time of the application to select the time axis for the user’s application.
7. The method of claim 1, wherein the configuration of the software application permits a rendering of a time for the application from one or more of the multiple time axes.
8. A system comprising:
a module to configure a software application with multiple time axes to represent one or more time elements; and further
a module to configure the software application to present a user with a selection of one or more of the multiple time axes.
9. The system of claim 8, further comprising a module to configure the software application with a time zone code and a daylight savings time indicator, thereby providing the software application with an ability to differentiate a duplicate hour in transitioning between daylight savings time and standard time.
10. The system of claim 8, wherein
the one or more time axes include a time portion and a date portion; and
the multiple time axes comprise one or more of a twenty four hour day time axis, a Gregorian date axis, a UTC time axis, a local date and time axis offset from the UTC time axis, a local date and time axis including time zone data and a daylight savings time indicator, and a date and time axis independent of a time zone.
11. The system of claim 10, wherein one or more of the multiple time axes further comprises a timepoint to indicate a dimensionless point in time.
12. The system of claim 8, wherein the configuration of the software application permits an exchange of time information via a specification of the one or more multiple time axes.
13. The system of claim 8, further comprising:
a module to configure the software application so as to enable a user at run time of the application to select the time axis for the user’s application.
14. The system of claim 8, wherein the configuration of the software application permits a rendering of a time for the application from one or more of the multiple time axes.
15. A machine-readable medium having instructions for executing a process comprising:
configuring a software application with multiple time axes to represent one or more time elements; and further
configuring the software application to present a user with a selection of one or more of the multiple time axes.
16. The machine-readable medium of claim 15, further comprising instructions for configuring the software application with a time zone code and a daylight savings time indicator, thereby providing the software application with an ability to differentiate a duplicate hour in transitioning between daylight savings time and standard time.
17. The machine-readable medium of claim 15, wherein
the one or more time axes include a time portion and a date portion; and
the multiple time axes comprise one or more of a twenty four hour day time axis, a Gregorian date axis, a UTC time axis, a local date and time axis offset from the UTC time axis, a local date and time axis including time zone data and a daylight savings time indicator, and a date and time axis independent of a time zone.
18. The machine-readable medium of claim 17, wherein one or more of the multiple time axes further comprises a timepoint to indicate a dimensionless point in time.
19. The machine-readable medium of claim 15, wherein the configuration of the software application permits an exchange of time information via a specification of the one or more multiple time axes; and further
wherein the configuration of the software application permits a rendering of a time for the application from one or more of the multiple time axes.
20. The machine-readable medium of claim 15, further comprising instructions for:
configuring the software application so as to enable a user at run time of the application to select the time axis for the user’s application.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor memory device, comprising:
a memory cell array for storing rows of data having row addresses;
a cache for temporarily storing at least one row of data having an arbitrary row address from among said row addresses;
a plurality of sense amplifiers coupled to said memory cell array and said cache, for amplifying data stored in said memory cell array at a first rate, and amplifying data stored in said cache at a second rate faster than said first rate; and
a data bus coupled to said sense amplifiers and said cache, for input and output of data.
2. The semiconductor memory device of claim 1, comprising a tag circuit coupled to said cache, for storing row addresses of the data stored in said cache.
3. The semiconductor memory device of claim 1, wherein said semiconductor memory device is a dynamic random-access memory, requiring periodic refreshing of data stored in said memory cell array, and said cache stores first data having one row address while said sense amplifiers refresh second data having another address by amplifying said second data in said memory cell array.
4. The semiconductor memory device of claim 1, further comprising switching elements for disconnecting said cache and said data bus from said sense amplifiers, wherein said semiconductor memory device is a dynamic random-access memory, requiring periodic refreshing of data stored in said memory cell array, and said-sense amplifiers amplify and thereby refresh first data stored in said memory cell array while second data are transferred between said cache and said data bus.
5. The semiconductor memory device of claim 1, comprising write buffers coupled to said sense amplifiers, for receiving first data stored in said cache, storing said first data while said first data are replaced in said cache by second data from said memory cell array, and transferring said first data to said memory cell array after said first data have been thus replaced.
6. A semiconductor memory device, comprising:
a rectangular array of memory cells disposed in intersecting rows and columns, for storing data;
a plurality of bit lines extending parallel to said columns and coupled to the memory cells in respective columns, for transporting data to and from said memory cells;
a plurality of word lines extending parallel to said rows and coupled to the memory cells in respective rows, for controlling transfer of data between said memory cells and said bit lines;
a row of first switching elements coupled to respective bit lines;
a plurality of sense lines coupled to respective first switching elements, for transferring data via said first switching elements to and from said bit lines;
a row of sense amplifiers coupled to said of sense lines, for amplifying data on said sense lines;
a row of second switching elements coupled to respective sense lines;
a data bus for input and output of data;
a plurality of column data lines coupled to respective second switching elements, for interfacing said sense lines to said data bus;
a cache having at least one row of cache cells coupled to said column data lines, for storing data transferred from an arbitrary row of said memory cells; and
a tag circuit coupled to said cache, for storing, for each said row of cache cells, a row address indicating which row of said memory cells has data stored in said row of cache cells, and controlling transfer of data between said row of cache cells and said column data lines responsive to said row address.
7. The memory device of claim 6, wherein:
said bit lines are grouped into complementary pairs, with one complementary pair of bit lines per column;
said sense lines are grouped into corresponding complementary pairs; and
said column data lines are grouped into corresponding complementary pairs.
8. The memory device of claim 7, wherein each of said cache cells comprises:
a third switching element coupled to one of said column data lines and switched on and off by said tag circuit; and
a storage element coupled to said switching element.
9. The memory device of claim 8, wherein:
said third switching element is a transistor; and
said storage element is a capacitor having one electrode coupled to said transistor and another electrode coupled to a fixed potential.
10. The memory device of claim 7, wherein each of said cache cells comprises:
a third switching element coupled to one of said column data lines and switched on and off by said tag circuit;
a fourth switching element coupled to another one of said column data lines and switched on and off by said tag circuit; and
a storage element coupled in series between said third switching element and said fourth switching element.
11. The memory device of claim 7, wherein each of said sense amplifiers is supplied with two different fixed potentials for use in amplifying data on said complementary pairs of sense lines, further comprising:
sense-line equalizing circuits coupled to respective complementary pairs of sense lines, for equalizing said sense lines to a third potential intermediate between said two different fixed potentials;
a sense-amplifier equalizing circuit coupled to said row of sense amplifiers, for supplying said sense amplifiers with said third potential in place of said two different fixed potentials; and
a delay circuit coupled to said sense-amplifier equalizing circuit, for delaying supply of said third potential to said sense amplifiers until a certain time after equalization of said sense lines has begun.
12. The memory device of claim 11, also comprising a hitmiss detector coupled to said delay circuit, for preventing the supply of said third potential to said sense amplifiers prior to transfer of data from said cache cells to said sense lines.
13. The memory device of claim 12, wherein said hitmiss detector comprises:
a hit detector for detecting, from an output of said tag circuit, access to said cache cells, and generating a first signal;
a miss detector for detecting, from an output of said tag circuit, access to said memory cells, and generating a second signal that activates said sense-amplifier equalizing circuit via said delay circuit; and
a logic gate for combining said first signal and said second signal to produce a third signal, which activates said sense-line equalizing circuits both when access to said cache cells is detected and when access to said memory cells is detected.
14. The memory device of claim 7, further comprising a row of write buffers coupled between respective complementary pairs of sense lines, for storing data to be copied back from said cache cells to said memory cell array, while other data are transferred from said memory cell array to said cache cells.
15. The memory device of claim 14, wherein each of said write buffers comprises a switching element, a storage element, and another switching element coupled in series between a complementary pair of said sense lines.
16. The memory device of claim 14, comprising a transfer control circuit for turning off said first switching elements after data have been transferred from said bit lines to said sense lines, but before said sense amplifiers have finished amplifying said data.
17. The memory device of claim 16, wherein said transfer control circuit comprises:
a control circuit for generating a first transfer signal for controlling said first switching elements when data are transferred unidirectionally from said bit lines to said sense lines;
a logic circuit for receiving said first transfer signal, also receiving a sense amplifier enable signal that enables and disables said sense amplifiers, and generating a second transfer signal that is active if and only if said first transfer signal is active and said sense amplifier enable signal is inactive, said second transfer signal being used to control said first switching elements.
18. The memory device of claim 6, wherein said memory cells are dynamic memory cells that are refreshed periodically by said sense amplifiers, comprising a refresh control circuit coupled to said tag circuit, for determining whether data for a row of memory cells to be refreshed are stored in said cache, and if so, refreshing said row of memory cells by transferring data from said cache to said row of memory cells.
19. The memory device of claim 18, wherein said refresh control circuit generates:
a first set of refresh timing signals that turn said first switching elements on and said second switching elements off, thereby permitting data in said memory cells to be refreshed by said sense amplifiers while data are transferred between said column data lines and said data bus; and
a second set of refresh timing signals that turn on both said first switching elements and said second switching elements, and cause data to be transferred from said cache to said sense lines, amplified by said sense amplifiers, then transferred via said bit lines to said memory cells.
20. The memory device of claim 19, wherein said refresh control circuit comprises:
a refresh timing generator for generating said first set of refresh timing signals and said second set of refresh timing signals;
a multiplexer coupled to said tag circuit, for providing a refresh address to said tag circuit;
a logic circuit coupled to said tag circuit, for deciding whether said refresh address matches a row address of data stored in said cache; and
a switch coupled to and controlled by said logic circuit, for selecting one set of refresh timing signals generated by said refresh timing generator.
21. The memory device of claim 6, comprising three-level driver circuits for driving said word lines and said first switching elements at a first active level to transfer data from said sense lines to said memory cells, and at a second active level lower than said first active level to transfer data from said memory cells via said sense lines to said cache cells.
22. The memory device of claim 7, wherein:
said cache cells are disposed in a cache element area; and
the second switching elements coupled to each complementary pair of sense lines are disposed on opposite sides of said cache element area.
23. The memory device of claim 22, wherein said data bus comprises a complementary pair read data lines disposed on respective opposite sides of said cache element area, and a complementary pair of write data lines also disposed on respective opposite sides of said cache element area.
24. The memory device of claim 7, wherein:
said cache cells are disposed in a cache element area; and
both of the second switching elements coupled to each complementary pair of sense lines are disposed on one side of said cache element area.
25. The memory device of claim 24, wherein said data bus comprises a complementary pair of read data lines both disposed on one side of said cache element area, and a complementary pair of write data lines both disposed on another side of said cache element area.
26. The memory device of claim 7, wherein:
said cache cells are disposed in a cache element area;
said cache element area also has dummy cells which are not coupled to said column data lines and are not coupled to said sense lines; and
in their combined arrangement, said cache cells and said dummy cells match row and column pitches of said memory cells in said memory cell array.
27. The memory device of claim 26, wherein:
each complementary pair of said column data lines is disposed between a complementary pair of said sense lines;
said cache cells are disposed between complementary column data lines; and
said dummy cells are disposed between said column data lines and said sense lines.
28. A semiconductor memory device, comprising:
a rectangular array of memory cells disposed in intersecting rows and columns, for storing data;
a plurality of bit lines extending parallel to said columns and coupled to the memory cells in respective columns, for transporting data t o and from said memory cells;
a plurality of word lines extending parallel to said rows and coupled to the memory cells in respective rows, for controlling transfer of data between said memory cells and said bit lines;
a row of first switching elements coupled to respective bit lines;
a plurality of sense lines coupled to respective first switching elements, for transferring data via said first switching elements to and from-said bit lines;
a row of sense amplifiers coupled to said sense lines, for amplifying the data on said sense lines;
a row of cache cells coupled to said sense lines, for storing data of an arbitrary row of said memory cells; and
a tag circuit coupled to said row of cache cells, for storing a row address indicating the row of said memory cells having data stored in said cache cells, and controlling transfer of data between said cache cells and said sense lines responsive to said row address.
29. The memory device of claim 28, comprising:
a plurality of rows of cache cells as described in claim 31, for storing data of an arbitrary plurality of rows of said memory cells.
30. The memory device of claim 29, wherein said tag circuit comprises a plurality of tag memories for storing row addresses of data stored in corresponding rows of cache cells.
31. The memory device of claim 29, wherein:
said memory cell array is divided into left and right banks;
said sense lines are switchably coupled to both said left and right banks; and
any row of cache cells in said plurality of rows of cache cells can store data of either of said left and right banks.
32. The memory device of claim 28, wherein:
said bit lines are grouped into complementary pairs, with one complementary pair of bit lines per column; and
said sense lines are grouped into corresponding complementary pairs.
33. The memory device of claim 32, wherein each of said cache cells comprises:
a second switching element coupled to one of said sense lines and switched on and off by said tag circuit; and
a storage element coupled to said second switching element.
34. The memory device of claim 33, wherein:
said second switching element is a transistor; and
said storage element is a capacitor having one electrode coupled to said transistor and another electrode coupled to a fixed potential.
35. The memory device of claim 32, wherein each of said cache cells comprises:
a second switching element coupled to one of said sense lines and switched on and off by said tag circuit;
a third switching element coupled to another one of said sense lines and switched on and off by said tag circuit; and
a storage element coupled in series between said second switching element and said third switching element.
36. The memory device of claim 28, wherein:
said memory cells are dynamic memory cells that are refreshed periodically by said sense amplifiers; and
said tag circuit prevents transfer of data between said cache cells and said sense lines while said sense amplifiers are refreshing said memory cells.
37. The memory device of claim 32, wherein each of said sense amplifiers is supplied with two different fixed potentials for use in amplifying data on said complementary pairs of sense lines, further comprising:
sense-line equalizing circuits coupled to respective complementary pairs of sense lines, for equalizing said sense lines to a third potential intermediate between said two different fixed potentials;
a sense-amplifier equalizing circuit coupled to said row of sense amplifiers, for supplying said sense amplifiers with said third potential in place of said two different fixed potentials; and
a delay circuit coupled to said sense-amplifier equalizing circuit, for delaying supply of said third potential to said sense amplifiers until a certain time after equalization of said sense lines has begun.
38. The memory device of claim 37, also comprising a hitmiss detector coupled to said sense-amplifier equalizing circuit, for preventing the supply of said third potential to said sense amplifiers prior to transfer of data from said cache cells to said sense lines.
39. The memory device of claim 38, wherein said hitmiss detector comprises:
a hit detector for detecting, from an output of said tag circuit, access to said cache cells, and generating a first signal;
a miss detector for detecting, from an output of said tag circuit, access to said memory cells, and generating a second signal that activates said sense-amplifier equalizing circuit via said delay circuit; and
a logic gate for combining said first signal and said second signal to produce a third signal, which activates said sense-line equalizing circuits both when access to said cache cells is detected and when access to said memory cells is detected.
40. In a semiconductor memory device having word lines, rows of memory cells coupled to respective word lines, sense lines, sense amplifiers coupled to said sense lines, cache cells coupled to said sense lines, and a data bus, a method of executing a memory access cycle, comprising the steps of:
receiving a row address designating a row of memory cells;
determining if data of said row of memory cells are currently present in said sense amplifiers and said cache cells;
transferring said data from said cache cells to said sense lines, if said data are currently present in said cache cells but not in said sense amplifiers, and amplifying the data thus transferred;
transferring said data from said memory cells to said sense lines, if said data are currently present in neither said cache cells nor said sense amplifiers, and amplifying the data thus transferred;
receiving at least one column address and transferring data between corresponding sense lines and said data bus, thereby completing said memory cycle; and
leaving said sense amplifiers enabled when said memory cycle ends, so that said sense amplifiers continue to hold amplified data of the row of memory cells designated by said row address.
41. The method of claim 40, comprising the further steps of:
activating a word line corresponding to said row address;
transferring amplified data from said sense lines to the memory cells coupled to said word line; and
leaving said word line active when said memory cycle ends.
42. The method of claim 40, wherein the step of transferring data from said memory cells to said sense lines comprises the further steps of:
disabling said sense amplifiers;
interconnecting pairs of said sense lines;
waiting a certain time, thus allowing charge on said sense lines to discharge into said sense amplifiers; then
supplying a fixed potential to said sense lines and said sense amplifiers.
43. The method of claim 40, wherein the step of transferring data from said cache cells to said sense lines comprises the further steps of:
disabling said sense amplifiers;
interconnecting pairs of said sense lines;
waiting a certain time, thus allowing charge on said sense lines to discharge into said sense amplifiers; then
supplying a fixed potential to said sense lines but not to said sense amplifiers.
44. In a semiconductor memory device having word lines, rows of memory cells coupled to respective word lines, sense lines, sense amplifiers coupled to said sense lines, column data lines coupled to said sense lines, cache cells coupled to said column data lines, and a data bus, a method of refreshing said memory cells, comprising the steps of:
receiving a row address corresponding to data stored in said cache cells;
transferring said data from said cache cells via said column data lines to said sense lines, and amplifying the data thus transferred;
disconnecting said column data lines from said sense lines, thereby leaving amplified data on said column data lines;
activating a first word line;
using said sense amplifiers to refresh the memory cells coupled to said first word line; and
receiving at least one column address and transferring data between corresponding column data lines and said data bus, while said sense amplifiers are refreshing said memory cells.
45. The method of claim 44, comprising the further steps of:
disabling said sense amplifiers after said memory cells have been refreshed;
coupling said column data lines to said sense lines again; and
enabling said sense amplifiers, thereby again amplifying the data on said column data lines.
46. The method of claim 45, comprising the further steps of:
deactivating said first word line after said memory cells have been refreshed;
activating a second word line corresponding to said row address; and
transferring data from said column data lines via said sense lines to the memory cells coupled to said second word line.
47. In a semiconductor memory device having word lines, bit lines, memory cells coupled to said word lines and bit lines, sense lines, sense amplifiers coupled to said sense lines, write buffers coupled to said sense lines, column data lines coupled to said sense lines, cache cells coupled to said column data lines, and a data bus, a method of executing a cache load cycle, comprising the steps of:
receiving a row address not corresponding to data stored in any of said cache cells;
coupling said bit lines to said sense lines;
activating a word line corresponding to said row address;
transferring data from memory cells coupled to said word line via said bit lines to said sense lines;
amplifying the data on said sense lines;
coupling said column data lines to said sense lines;
transferring the data on said sense lines via said column data lines to said cache cells; and
receiving at least one column address and transferring data between said column data lines and said data bus, thereby completing said memory cycle.
48. The method of claim 47, wherein said sense amplifiers are left enabled and when said cache load cycle ends.
49. The method of claim 47, comprising the further steps of:
disconnecting said bit lines from said sense lines before amplification of the data on said sense lines is completed;
deactivating said word line; and
precharging said bit lines to a fixed potential.
50. The method of claim 47, wherein the step of transferring data from said memory cells to said sense lines comprises the further steps of:
disabling said sense amplifiers;
interconnecting pairs of said sense lines;
waiting a certain time, thus allowing charge on said sense lines to discharge into said sense amplifiers; then
supplying a fixed potential to said sense lines and said sense amplifiers.
51. In a semiconductor memory device having word lines, bit lines, memory cells coupled to said word lines and bit lines, sense lines, sense amplifiers coupled to said sense lines, write buffers coupled to said sense lines, column data lines coupled to said sense lines, cache cells coupled to said column data lines, and a data bus, a method of executing a cache hit cycle, comprising the steps of:
receiving a row address corresponding to data stored in said cache cells:
transferring data from said cache cells via said column data lines to said sense lines;
amplifying the data on said sense lines and said column data lines; and
receiving at least one column address and transferring data between said column data lines and a data bus, thereby completing said cache hit cycle.
52. The method of claim 51, wherein said sense amplifiers are left enabled and when said cache hit cycle ends.
53. The method of claim 51, wherein said bit lines are left disconnected from said sense lines throughout said cache hit cycle, and data are not transferred to said memory cells.
54. The method of claim 51, wherein the step of transferring data from said cache cells to said sense lines comprises the further steps of:
disabling said sense amplifiers;
interconnecting pairs of said sense lines;
waiting a certain time, thus allowing charge on said sense lines to discharge into said sense amplifiers; then
supplying a fixed potential to said sense lines but not to said sense amplifiers.
55. In a semiconductor memory device having word lines, bit lines, memory cells coupled to said word lines and bit lines, sense lines, sense amplifiers coupled to said sense lines, write buffers coupled to said sense lines, column data lines coupled to said sense lines, at least one row of cache cells coupled to respective column data lines, and a data bus, a method of executing a cache replace cycle, comprising the steps of:
receiving a row address not corresponding to data not stored in any of said cache cells;
selecting a row of cache cells;
transferring data from said row of cache cells to said write buffers, with amplification by said sense amplifiers;
transferring data from said memory cells via said sense lines to said column data lines and said row of cache cells, with amplification by said sense amplifiers;
disconnecting said column data lines from said sense lines;
receiving at least one column address and transferring data between corresponding column data lines and said data bus; and
transferring data from said write buffers to said memory cells, with amplification by said sense amplifiers.
56. The method of claim 55, wherein transferring data between said column data lines and said data bus and transferring data from said write buffers to said memory cells are carried out concurrently.
57. The method of claim 55, comprising the further steps of:
coupling said column data lines to said sense lines, after transferring said data from said write buffers to said memory cells; and
amplifying the data on said column data lines again.
58. The method of claim 55, wherein said sense amplifiers are left enabled when said cache replace cycle ends.
59. The method of claim 55, wherein the step of transferring data from said memory cells comprises:
coupling said bit lines to said sense lines;
activating a first word line corresponding to said row address, thereby transferring said data from the memory cells coupled to said first word line to said sense lines; and
disconnecting said bit lines from said sense lines when said data have been transferred to said sense lines, before amplification of said data is completed.
60. The method of claim 59, comprising the further steps of:
deactivating said first word line;
precharging said bit lines to a fixed potential;
activating a second word line corresponding to the data transferred from said row of cache cells to said write buffer;
deactivating said second word line after data have been transferred from said write buffer to the memory cells coupled to said second word line; and
precharging said bit lines to said fixed potential again.
61. In a semiconductor memory device having word lines, bit lines, memory cells coupled to said word lines and bit lines, sense lines, sense amplifiers coupled to said sense lines, column data lines coupled to said sense lines, cache cells coupled to said column data lines, and a data bus, a method of refreshing said memory cells, comprising the steps of:
obtaining a refresh address;
determining whether said refresh address corresponds to data stored in said cache cells;
transferring data from said cache cells via said column data lines, said sense lines, and said bit lines to said memory cells, with amplification by said sense amplifiers, if said refresh address corresponds to data stored in said cache cells; and
disconnecting said column data lines from said sense lines and using said sense amplifiers to refresh said memory cells, if said refresh address does not correspond to data stored in said cache cells.
62. The method of claim 61, wherein said cache cells are organized into at least two rows of cache cells, and the step of transferring data from said cache cells comprises:
selecting a first row of cache cells corresponding to said refresh address;
transferring data from said first row of cache cells to said column data lines; transferring data from said column data lines to said sense lines;
amplifying the data on said sense lines;
disconnecting said column data lines from said sense lines;
transferring data from said sense lines to said bit lines;
receiving a row address corresponding to a second row of cache cells different from said first row of cache cells;
transferring data from said second row of cache cells to said column data lines; and
receiving at least one column address and transferring data between corresponding column data lines and said data bus.
63. The method of claim 62, wherein transferring data from said second row of cache cells to said column data lines and transferring data between said column data lines and said data bus are carried out concurrently.
64. The method of claim 61, comprising the further steps of:
coupling said column data lines to said sense lines after said memory cells have been refreshed;
transferring data from said column data lines to said sense lines; and
amplifying the data on said column data lines and said sense lines.