1. An apparatus comprising:
a bulk substrate;
a fin structure in direct contact with and extending from the bulk substrate;
an oxide layer formed over the fin structure and over the bulk substrate, wherein the oxide layer is in direct contact with both the fin structure and the bulk substrate and wherein a top surface of the oxide layer is substantially planar over both the fin structure and the bulk substrate; and
a semiconductor body formed on the oxide layer proximate to and in alignment with the fin structure, wherein the semiconductor body and the fin structure are both formed from the same material as the bulk substrate and wherein the oxide layer isolates the semiconductor body from the fin structure.
2. The apparatus of claim 1, wherein the material comprises silicon.
3. The apparatus of claim 1, wherein the material comprises silicon alloyed with a second material selected from the group consisting of germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and gallium antimonide.
4. The apparatus of claim 1, wherein the oxide layer comprises silicon dioxide.
5. An apparatus comprising:
a bulk substrate;
a fin structure in direct contact with and extending from the bulk substrate;
an oxide layer formed atop the fin structure; and
a semiconductor body formed atop the oxide layer, wherein the oxide layer is formed by a thermal oxidation process that consumes a portion of the fin structure.
6. The apparatus of claim 5, wherein the fin structure comprises silicon, the bulk substrate comprises silicon, the semiconductor body comprises silicon, and the oxide layer comprises silicon dioxide.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for generating a random number, comprising the steps of: deriving from an input signal to a flip-flop a marking signal including decorrelating said marking signal to noise, wherein said input signal has a first binary value and a second binary value and wherein a value of said marking signal is said first binary value for approximately half of occurrences of said first binary value in said input signal and is said second binary value for approximately half of occurrences of said first binary value in said input signal; operating said flip-flop in a meta-stable state; and generating a random bit from the marking signal based on the occurrence of the meta-stable state.
2. The method of claim 1, wherein said decorrelating is performed by at least one linear feedback shift register.
3. The method of claim 2, wherein said linear feedback shift register provides a sufficient number of bits to decrease the chance of correlation.
4. The method of claim 2, wherein said linear feedback shift register (LFSR) provides a sufficient number of bits to reduce any bias in the LFSR output.
5. The method of claim 2, wherein said linear feedback shift register has a compensation circuit that removes bias from the generated random bits.
6. The method of claim 1, wherein said decorrelating is performed by a collection of linear feedback shift registers.
7. The method of claim 1, wherein said flip-flop is placed in said meta-stable state by violating a set-up time of said flip-flop.
8. The method of claim 1, wherein said flip-flop is placed in said meta-stable state by violating a hold time of said flip-flop.
9. The method of claim 1, wherein said generating step further comprises the step of generating a mistake signal if an output of said flip-flop does not match an applied input.
10. The method of claim 9, wherein to mistake signal causes a random bit to be acquired based on the marking input.
11. The method of claim 1, further comprising the step of synchronizing an output of said flip-flop with a local clock source.
12. The method of claim 1, further comprising the step of collecting a plurality of said random bits to produce a random number.
13. The method of claim 1, wherein said first binary value is zero and said second binary value is one.
14. The method of claim 1, wherein said first binary value is one and said second binary value is zero.
15. The method of claim 1, further comprising the step of releasing collected bits from a shift register to generate said random bit.
16. A method for generating a random number, comprising the steps of: deriving from an input signal to a flip-flop a marking signal, including decorrelating said marking signal to noise, wherein said input signal has a first binary value and a second binary value and wherein a value of said marking signal is said first binary value for approximately half of occurrences of said first binary value in said input signal and is said second binary value for approximately half of occurrences of said first binary value in said input signal; operating said flip-flop in a meta-stable state; and generating a random bit from the marking signal based on the occurrence of said meta-stable state.
17. The method of claim 16, wherein said decorrelating is performed by a linear feedback shift register.
18. The method of claim 17, wherein said linear feedback shift register provides a sufficient number of bits to decrease the chance of correlation.
19. The method of claim 17, wherein said linear feedback shift register (LFSR) provides a sufficient number of bits to reduce any bias in the LFSR output.
20. The method of claim 17, wherein said linear feedback shift register has a compensation circuit that removes bias from the generated random number.
21. The meted of claim 16, wherein said decorrelating is performed by a collection of linear feedback shift registers.
22. The method of claim 16, wherein said generating step further comprises the step of generating a mistake signal if an output of said flip-flop does not match an applied input.
23. The method of claim 16, further comprising the step of collecting a plurality of said random bits to produce a random number.
24. A random number generator, comprising: a flip-flop operated in a meta-stable state; a marking circuit for deriving from an input signal to a flip-flop a marking signal, including at least one linear feedback shift register that decorrelates said marking signal to noise, wherein said input signal has a first binary value and a second binary value and wherein a value of said marking signal is said first binary value for approximately half of occurrences of said first binary value in said input signal and is said second binary value for approximately half of occurrences of said first binary value in said input signal; and means for generating a random bit from the marking signal based on the occurrence of the meta-stable state.
25. The random number generator of claim 24, wherein said first binary value is zero and said second binary value is one.
26. The random number generator of claim 24, wherein said first binary value is one and said second binary value is zero.
27. The random number generator of claim 24, wherein said one or more linear feedback shift registers provide a sufficient number of bits to decrease the chance of correlation.
28. The random number generator of claim 24, wherein said one or more linear feedback shift registers (LFSRs) provide a sufficient number of bits to reduce any bias in the LFSR output.
29. The random number generator of claim 24, wherein said one or more linear feedback shift registers has a compensation circuit that removes bias from the generated random number.
30. A random number generator, comprising: a flip-flop operated in a meta-stable state; a marking circuit for deriving from an input signal to a flip-flop a marking signal, including one or more linear feedback shift registers that decorrelate said marking signal to noise, wherein said input signal has a first binary value and a second binary value and wherein a value of said marking signal is said first binary value for approximately half of occurrences said first binary value in said input signal and is said second binary value for approximately half of occurrences of said first binary value in said input signal; and means for generating a random bit from the marking signal based on the occurrence of the meta-stable state.
31. The random number generator of claim 30, wherein said one or more linear feedback shift registers provide a sufficient number of bits to decrease the chance of correlation.
32. The random number generator of claim 30, wherein said one or more linear feedback shift registers (LFSRs) provide a sufficient number of bits to reduce any bias in the LFSR output.
33. The random number generator of claim 30, wherein said one or more linear feedback shift registers has a compensation circuit that removes bias from the generated random number.