1. A reception device configured to receive a transmission signal adhering to a communications protocol, wherein a transmission device sends reception data to the reception device, the reception device comprising:
means for receiving the transmission signal;
means for evaluating the received transmission signal;
means for emitting a bit sequence received in the transmission signal, wherein the bit sequence contains bits of reception data transmitted from the transmission device and bits of interference caused by an interference to the transmission signals;
means for checking whether the received bit sequence infringes a rule of the communications protocol;
wherein the reception device is designed to continue with the reception of the transmission signal and the checking of the received bit sequence following the occurrence of an infringement of the communications protocol; and
means for checking whether a first segment of bits of the received bit sequence are already received before an expiry of a lead period that starts from the start of a reception period, wherein a first rule of the communications protocol is infringed, and wherein the reception device rejects the first segment of bits of the received bit sequence and continues to receive the transmission signal and to check another segment of bits of the received bit sequence that are received following expiry of the lead period.
2. A reception device as claimed in claim 1, further comprising:
means for emitting communication error information indicating an infringed rule in response to an infringement of a rule of the communications protocol.
3. A reception device as claimed in claim 2, further comprising:
means for checking whether, starting from the range of a reception period, a maximum reception period is already expired;
means for emitting exceeding-of-reception-period information in response to the expiration of the maximum reception period; and
means for emitting communication error information in response to a detection of an infringement of the communications protocol during the reception period.
4. A reception device as claimed in claim 3, further comprising means for determining the reception period that is already passed, wherein a measurement is interrupted by a counter means when a further bit is received in the transmission signal, and wherein the measurement is resumed by the counter means when an infringement of a rule of the communications protocol is established by the checking means.
5. A reception device as claimed in claim 2, further comprising:
means for storing the received bit sequence emitted by the evaluation means; and
means for storing detected communication error information.
6. A reception device as claimed in claim 1, further comprising means for providing the reception device in a base station, wherein the reception device enables contactless communication with at least one transponder forming the transmission device.
7. A reception method of receiving a transmission signal that adheres to a communications protocol, the reception method comprising:
receiving at a reception device a transmission signal from a transmission device, wherein the reception device comprises processing and storage means for performing operations of the reception method;
evaluating the received transmission signal;
emitting a bit sequence received in the transmission signal, wherein the bit sequence contains bits of reception data transmitted from the transmission device and bits of interference caused by an interference to the transmission signal;
checking whether the received bit sequence infringes a rule of the communications protocol;
continuing the reception of the transmission signals at the reception device and the checking of the received bit sequence in response to an infringement of the communications protocol; and
checking the received bit sequence as to whether the first bits of the received bit sequence are already received before an expiry of a lead period that starts from a start of a reception period and continuing to receive the transmission signal and to check the bits of the received bit sequence received following expiry of the lead period, wherein a first rule of the communications protocol is infringed, and wherein the bits of the received bit sequence received before the expiry of lead period are rejected.
8. A reception method as claimed in claim 7, further comprising emitting communication error information, wherein the communication error information indicates an infringement of a rule of the communications protocol.
9. A reception method as claimed in claim 8, further comprising:
checking, from the start of a reception period, whether a maximum reception period is already expired;
emitting exceeding-of-reception-period information in response to the expiration of the maximum reception period; and
emitting communication error information in response to a detection of an infringement of the communications protocol during the reception period.
10. A reception method as claimed in claim 9, further comprising determining that the reception period is already passed, wherein a measurement is interrupted when a further bit is received in the transmission signal, and wherein the measurement is continued when the infringement of a rule of the communications protocol is established.
11. A reception device configured to receive a transmission signal adhering to a communications protocol, wherein a transmission device sends reception data to the reception device, the reception device comprising:
means for receiving the transmission signal;
means for evaluating the received transmission signal;
means for emitting a bit sequence received in the transmission signal, wherein the bit sequence contains bits of reception data transmitted from the transmission device and bits of interference caused by an interference to the transmission signals;
means for checking whether the received bit sequence infringes a rule of the communications protocol;
wherein the reception device is designed to continue with the reception of the transmission signal and the checking of the received bit sequence following the occurrence of an infringement of the communications protocol; and
means for checking the received bit sequence as to whether redundancy information contained at a predetermined bit position in valid reception data identifies defective bits in the received bit sequence, wherein a second rule of the communications protocol is infringed, and wherein the reception device rejects the bits of the received bit sequence identified as defective continues to receive the transmission signal and to check a subsequent received bit sequence.
12. A reception device as claimed in claim 11, further comprising:
means for emitting communication error information indicating an infringed rule in response to an infringement of a rule of the communications protocol.
13. A reception device as claimed in claim 12, further comprising:
means for checking whether, starting from the range of a reception period, a maximum reception period is already expired;
means for emitting exceeding-of-reception-period information in response to the expiration of the maximum reception period; and
means for emitting communication error information in response to a detection of an infringement of the communications protocol during the reception period.
14. A reception device as claimed in claim 13, further comprising means for determining the reception period that is already passed, wherein a measurement is interrupted by a counter means when a further bit is received in the transmission signal, and wherein the measurement is resumed by the counter means when an infringement of a rule of the communications protocol is established by the checking means.
15. A reception device as claimed in claim 12, further comprising:
means for storing the received bit sequence emitted by the evaluation means; and
means for storing detected communication error information.
16. A reception device as claimed in claim 11, further comprising means for providing the reception device in a base station, wherein the reception device enables contactless communication with at least one transponder forming the transmission device.
17. A reception method of receiving a transmission signal that adheres to a communications protocol, the reception method comprising:
receiving at a reception device a transmission signal from a transmission device, wherein the reception device comprises processing and storage means for performing operations of the reception method;
evaluating the received transmission signal;
emitting a bit sequence received in the transmission signal, wherein the bit sequence contains bits of reception data transmitted from the transmission device and bits of interference caused by an interference to the transmission signal;
checking whether the received bit sequence infringes a rule of the communications protocol;
continuing the reception of the transmission signals at the reception device and the checking of the received bit sequence in response to an infringement of the communications protocol; and
checking as to whether redundancy information contained at a predetermined bit position in valid reception data identifies defective bits in the received bit sequence, wherein a second rule of the communications protocol is infringed, and wherein the bits of the received bit sequence identified as defective are rejected, and the reception of the transmission signal and the checking of the subsequent bit sequence received continue.
18. A reception method as claimed in claim 17, further comprising emitting communication error information, wherein the communication error information indicates an infringement of a rule of the communications protocol.
19. A reception method as claimed in claim 18, further comprising:
checking, from the start of a reception period, whether a maximum reception period is already expired;
emitting exceeding-of-reception-period information in response to the expiration of the maximum reception period; and
emitting communication error information in response to a detection of an infringement of the communications protocol during the reception period.
20. A reception method as claimed in claim 19, further comprising determining that the reception period is already passed, wherein a measurement is interrupted when a further bit is received in the transmission signal, and wherein the measurement is continued when the infringement of a rule of the communications protocol is established.
21. A reception device configured to receive a transmission signal adhering to a communications protocol, wherein a transmission device sends reception data to the reception device, the reception device comprising:
means for receiving the transmission signal;
means for evaluating the received transmission signal;
means for emitting a bit sequence received in the transmission signal, wherein the bit sequence contains bits of reception data transmitted from the transmission device and bits of interference caused by an interference to the transmission signals;
means for checking whether the received bit sequence infringes a rule of the communications protocol;
wherein the reception device is designed to continue with the reception of the transmission signal and the checking of the received bit sequence following the occurrence of an infringement of the communications protocol; and
means for checking the received bit sequence, as to whether a framebit sequence predetermined by the communications protocol is missing from a predetermined bit position in the received bit sequence, wherein a third rule of the communications protocol is infringed, and wherein the reception device rejects the bit sequence already received and continues to receive the transmission signal and to check a subsequent received bit sequence.
22. A reception device as claimed in claim 21, further comprising:
means for emitting communication error information indicating an infringed rule in response to an infringement of a rule of the communications protocol.
23. A reception device as claimed in claim 22, further comprising:
means for checking whether, starting from the range of a reception period, a maximum reception period is already expired;
means for emitting exceeding-of-reception-period information in response to the expiration of the maximum reception period; and
means for emitting communication error information in response to a detection of an infringement of the communications protocol during the reception period.
24. A reception device as claimed in claim 23, further comprising means for determining the reception period that is already passed, wherein a measurement is interrupted by a counter means when a further bit is received in the transmission signal, and wherein the measurement is resumed by the counter means when an infringement of a rule of the communications protocol is established by the checking means.
25. A reception device as claimed in claim 22, further comprising:
means for storing the received bit sequence emitted by the evaluation means; and
means for storing detected communication error information.
26. A reception device as claimed in claim 21, further comprising means for providing the reception device in a base station, wherein the reception device enables contactless communication with at least one transponder forming the transmission device.
27. A reception method of receiving a transmission signal that adheres to a communications protocol, the reception method comprising:
receiving at a reception device a transmission signal from a transmission device, wherein the reception device comprises processing and storage means for performing operations of the reception method;
evaluating the received transmission signal;
emitting a bit sequence received in the transmission signal, wherein the bit sequence contains bits of reception data transmitted from the transmission device and bits of interference caused by an interference to the transmission signal;
checking whether the received bit sequence infringes a rule of the communications protocol;
continuing the reception of the transmission signals at the reception device and the checking of the received bit sequence in response to an infringement of the communications protocol; and
checking as to whether a framebit sequence predetermined by the communications protocol is missing from a predetermined bit position in the received bit sequence, wherein a third rule of the communications protocol is infringed, and wherein the bits identified as defective in the received bit sequence are rejected, and the reception of the transmission signal and the checking of the subsequent bit sequence received continue.
28. A reception method as claimed in claim 27, further comprising emitting communication error information, wherein the communication error information indicates an infringement of a rule of the communications protocol.
29. A reception method as claimed in claim 28, further comprising:
checking, from the start of a reception period, whether a maximum reception period is already expired;
emitting exceeding-of-reception-period information in response to the expiration of the maximum reception period; and
emitting communication error information in response to a detection of an infringement of the communications protocol during the reception period.
30. A reception method as claimed in claim 29, further comprising determining that the reception period is already passed, wherein a measurement is interrupted when a further bit is received in the transmission signal, and wherein the measurement is continued when the infringement of a rule of the communications protocol is established.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1: An apparatus which comprises:
a multi-core processor and
at least one test control mechanism;
said multi-core processor and said test control mechanism having a configuration so as to allow testing of said multi-core processor.
2: The apparatus of claim 1, wherein said multi-core processor comprises at least two processor cores and at least one circuit comprising non-processor core logic.
3: The apparatus of claim 2, wherein said multi-core processor and said test control mechanism having a configuration so as to allow testing of at least two processor cores of said multi-core processor.
4: The apparatus of claim 2, wherein said at least one test control mechanism respectively comprises at least one test access port controller (TAPC) and a plurality of distributed data and control registers; wherein said plurality of distributed data and control registers are located both within said at least two processor cores and within said at least one circuit comprising non-core logic.
5: The apparatus of claim 4, wherein said at least one test control mechanism is substantially compliant with the IEEE 1149.1 specification.
6: The apparatus of claim 4, wherein said at least one test access port controller (TAPC) is located within said at least two processor cores.
7: The apparatus of claim 4, wherein said at least one test access port controller (TAPC) and at least one of said plurality of distributed data and control registers are coupled via an Integrated Test Bus (ITB).
8: The apparatus of claim 4, wherein said distributed test control mechanism is controllable, at least in part, by one of said at least one test access port controller (TAPC).
9: The apparatus of claim 8, wherein which of said at least one test access port controllers (TAPCS) controls said distributed test control mechanism is dynamically selectable during operation.
10: The apparatus of claim 2, wherein at least one of the said at least two processor cores comprises one test access port (TAP) which includes one test access port controller (TAPC), and a plurality of distributed data and control registers.
11: The apparatus of claim 10, wherein said test control mechanism and said at least two processor cores are coupled so as to provide multiple coupling arrangements, said multiple coupling arrangements being dynamically selectable during operation.
12: The apparatus of claim 11, wherein said multiple coupling arrangements are selected from a group consisting essentially of coupling said test access ports substantially in series, coupling said test access ports substantially in parallel and coupling said test access ports for substantially independent operation.
13: The apparatus of claim 10, wherein said at least one test control mechanism is arranged to allow at least one of said at least two processor cores’ said one test access port (TAP) to be externally visible from said multi-core processor.
14: The apparatus of claim 13, wherein said at least one test control mechanism is arranged to allow only one of said at least two processor cores’ said one test access port (TAP) to be externally visible from said multi-core processor.
15: The apparatus of claim 13, wherein said at least one test control mechanism is arranged to allow the selection of which at least one of said at least two processor cores’ said one test access port (TAP) is externally visible from said multi-core processor to occur dynamically.
16: The apparatus of claim 10, wherein said at least one test control mechanism is coupled to produce during operation an error signal if the output signals of said at least two processor cores’ said one test access port (TAP) are not substantially equivalent.
17: The apparatus of claim 2, wherein said at least one test control mechanism, said at least one processor core and said at least one circuit comprising non-processor core logic are further coupled so as to allow testing of said at least one circuit comprising non-processor core logic.
18: A system which comprises:
a computing platform, including:
a memory to store instructions;
a multi-core processor to process instructions which includes:
a plurality of processor cores;
at least one circuit comprising non-processor core logic and
a test control mechanism;
said multi-core processor and said test control mechanism having a configuration so as to allow testing of said plurality of processor cores.
19: The system of claim 18, wherein said multi-core processor and said test control mechanism are further arranged so as to allow testing of said at least one circuit comprising non-processor core logic.
20: The system of claim 18, wherein said test control mechanism comprises at least one test access port controller (TAPC) and a plurality of distributed data and control registers; wherein said plurality of distributed data and control registers are located both within said plurality of processor cores and within said at least one circuit comprising non-core logic.
21: The system of claim 20, wherein said at least one test control mechanism is substantially compliant with the IEEE 1149.1 specification.
22: The system of claim 20, wherein said at least one test access port controller (TAPC) is located within said plurality of two processor cores.
23: The system of claim 20, wherein said at least one test access port controller (TAPC) and at least one of said a plurality of distributed data and control registers are coupled via an Integrated Test Bus (ITB).
24: The system of claim 20, wherein said distributed test control mechanism is controlled, at least in part, by one of said at least one test access port controller (TAPC).
25: The system of claim 24, wherein which of said at least one test access port controllers (TAPCs) controls said distributed test control mechanism is be dynamically selected during operation.
26: The system of claim 18, wherein each of the said at least two processor cores comprises one test access port (TAP) which includes one test access port controller (TAPC), and a plurality of distributed data and control registers.
27: The system of claim 26, wherein said test control mechanism and said at least two processor cores are coupled so as to provide multiple coupling arrangements, said multiple coupling arrangements being dynamically selected during operation.
28: The system of claim 27, wherein said multiple coupling configurations are selected from a group consisting essentially of coupling said test access ports substantially in series, coupling said test access ports substantially in parallel, and coupling said test access ports for substantially independent operation.
29: The system of claim 26, wherein said test control mechanism is coupled to produce, during operation, a signal that indicates whether the output signals of said at least two processor cores’ said one test access port (TAP) are equivalent or substantially equivalent.
30: A method, comprising:
providing an indicator to identify a desired testing option;
based upon said desired testing option, dynamically routing signals between a plurality test access ports (TAPs);
wherein said plurality test access ports (TAPs) are part of a multi-core processor; said multi-processor core including a plurality of processor cores.
31: The method of claim 30, wherein the routing of said signals is selected from a group consisting essentially of coupling said test access ports substantially in series, coupling said test access ports substantially in parallel, and coupling said test access ports for substantially independent operation.
32: The method of claim 31, wherein providing an indicator to identify a desired testing option comprises storing control information in a register.
33: The method of claim 32, wherein storing control information in a register comprises shifting said data into the register in a serial fashion.
34: The method of claim 32, wherein storing control information in a register comprises a step in compliance with the operation of test data registers as described in the IEEE 1149.1 specification.
35: The method of claim 30, wherein dynamically routing signals between a plurality of test access ports (TAPs) comprises dynamically routing signals between a plurality of test access port controllers (TAPCs) and a plurality of distributed data and control registers.
36: The method of claim 30, wherein dynamically routing signals between a plurality of test access ports (TAPs) comprises only altering the routing of signals external to said plurality of processor cores.
37: The method of claim 30, which further comprises producing a signal that indicates whether the output signals of said at least two processor cores’ said one test access port (TAP) are equivalent or substantially equivalent