1. A circuit comprising:
a radio frequency (RF) switching device having a gate terminal, the RF switching device configured to receive an RF input signal and to pass an RF output signal if the RF switching device is activated;
a gate resistor coupled between the gate terminal and a control terminal, the control terminal configured to receive a control signal to activate the RF switching device; and
a helper circuit coupled in parallel with the gate resistor, the helper circuit configured to provide a temporary conductive path between the control terminal and the gate terminal in response to a state transition of the control signal, wherein the helper circuit includes:
a helper switching device coupled in parallel with the gate resistor, the helper switching device having a helper gate terminal;
a coupling capacitor coupled between the helper gate terminal and the control terminal to turn on the helper switching device in response to the state transition of the control signal; and
a discharge resistor coupled between the helper gate terminal and the gate terminal of the RF switching device to turn off the helper switching device when a voltage at the gate terminal is equal to a voltage at the control terminal.
2. The circuit of claim 1, wherein the helper circuit comprises an open circuit between the control terminal and the gate terminal of the RF switching device during a steady state of the control signal between state transitions.
3. The circuit of claim 1, wherein the RF switching device and the helper switching device comprise field-effect transistors.
4. The circuit of claim 1, wherein dimensions of the helper switching device are smaller than corresponding dimensions of the RF switching device by a factor of ten or more.
5. The circuit of claim 1, wherein the helper switching device is an enhancement type device.
6. The circuit of claim 1, wherein the gate terminal is a first gate terminal, the gate resistor is a first gate resistor, and the helper circuit is a first helper circuit, and wherein the RF switching device further includes a second gate terminal, and wherein the circuit further includes:
a second gate resistor coupled between the second gate terminal and the control terminal; and
a second helper circuit coupled in parallel with the second gate resistor, the second helper circuit configured to provide a conductive path between the control terminal and the second gate terminal in response to the state transition of the control signal.
7. The circuit of claim 6, wherein the helper switching device of the first helper circuit is a first helper switching device, wherein the helper gate terminal of the first helper switching device is a first helper gate terminal, wherein the first helper switching device further includes a second helper gate terminal, and wherein the first helper circuit further includes:
a first helper gate resistor coupled between the first helper gate terminal and a first node;
a second helper gate resistor coupled between the second helper gate terminal and the first node;
wherein the coupling capacitor is coupled between the first node and the control terminal; and
wherein the discharge resistor is coupled between the first node and the first gate terminal of the RF switching device.
8. The circuit of claim 7, wherein the first helper switching device further includes a helper drain terminal and a helper source terminal, and wherein the first helper circuit further includes a first feed-forward capacitor coupled between the first helper gate terminal and the helper drain terminal and a second feed-forward capacitor coupled between the second helper gate terminal and the helper source terminal.
9. A radio frequency (RF) switching apparatus, comprising:
an RF transistor having a gate terminal, a drain terminal and a source terminal, the RF transistor configured to receive an RF input signal at the drain terminal and to pass an RF output signal to the source terminal if the RF transistor is activated;
a gate resistor coupled between the gate terminal and a control terminal, the control terminal configured to receive a control signal to activate the RF transistor;
a helper transistor coupled in parallel with the gate resistor, the helper transistor having a helper gate terminal, a helper drain terminal, and a helper source terminal;
a coupling capacitor coupled between the helper gate terminal and the control terminal; and
a discharge resistor coupled between the helper gate terminal and the gate terminal of the RF transistor
wherein the coupling capacitor is configured to turn on the helper transistor in response to a state transition of the control signal to provide a conductive path between the control terminal and the gate terminal of the RF transistor; and
wherein the discharge resistor is configured to turn off the helper transistor when a voltage at the gate terminal is equal to a voltage at the control terminal.
10. The RF switching apparatus of claim 9, wherein the helper transistor comprises an open circuit between the control terminal and the gate terminal of the RF transistor during a steady state of the control signal between state transitions.
11. The RF switching apparatus of claim 9, wherein the helper gate terminal is a first helper gate terminal, wherein the helper transistor further comprises a second helper gate terminal, and wherein the apparatus further includes:
a first helper gate resistor coupled with the first helper gate terminal; and
a second helper gate resistor coupled with the second helper gate terminal.
12. The RF switching apparatus of claim 11, wherein the helper transistor, the coupling capacitor, the discharge resistor, and the first and second helper gate resistors are included in a first helper circuit, wherein the gate terminal is a first gate terminal, the gate resistor is a first gate resistor, and the RF transistor further comprises a second gate terminal, and wherein the apparatus further comprises:
a second gate resistor coupled between the second gate terminal and the control terminal; and
a second helper circuit coupled in parallel with the second gate resistor.
13. The RF switching apparatus of claim 11, wherein the RF transistor further includes a helper drain terminal and a helper source terminal, and wherein the apparatus further comprises a first feed-forward capacitor coupled between the first helper gate terminal and the helper drain terminal and a second feed-forward capacitor coupled between the second helper gate terminal and the helper source terminal.
14. The RF switching apparatus of claim 9, wherein the helper transistor is an enhancement type field-effect transistor.
15. A system, comprising:
a radio frequency (RF) power amplifier configured to amplify an RF signal; and
an RF switching module coupled with the RF power amplifier, the RF switching module including:
a radio frequency (RF) transistor having a gate terminal, an input terminal, and an output terminal, the RF transistor configured to receive the RF signal at the input terminal and to selectively pass the RF signal to the output terminal if the RF transistor is activated;
a control terminal configured to receive a control signal to activate the RF transistor;
a gate resistor coupled between the gate terminal and the control terminal; and
a helper circuit coupled in parallel with the gate resistor, the helper circuit configured to provide a temporary conductive path between the control terminal and the gate terminal in response to a state transition of the control signal, wherein the helper circuit includes:
a helper switching device coupled in parallel with the gate resistor, the helper switching device having a helper gate terminal;
a coupling capacitor coupled between the helper gate terminal and the control terminal to turn on the helper switching device in response to the state transition of the control signal; and
a discharge resistor coupled between the helper gate terminal and the gate terminal of the RF switching device to turn off the helper switching device when a voltage at the gate terminal is equal to a voltage at the control terminal.
16. The system of claim 15, wherein the gate terminal is a first gate terminal, the gate resistor is a first gate resistor, and the helper circuit is a first helper circuit, wherein the RF transistor further includes a second gate terminal, and wherein the system further includes:
a second gate resistor coupled between the second gate terminal and the control terminal; and
a second helper circuit coupled in parallel with the second gate resistor, the second helper circuit configured to provide a conductive path between the control terminal and the second gate terminal in response to the state transition of the control signal.
17. The circuit of claim 16, wherein the helper gate terminal is a first helper gate terminal, wherein the helper transistor further includes a second helper gate terminal, and wherein the first helper circuit further includes:
a first helper gate resistor coupled with the first helper gate terminal; and
a second helper gate resistor coupled with the second helper gate terminal.
18. The circuit of claim 16, further comprising a shunt capacitor coupled with the output terminal of the RF switching transistor, wherein RF transistor is configured to receive the amplified RF signal at the input terminal and to pass the amplified RF signal to the shunt capacitor if the RF transistor is activated.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming a dual damascene wiring pattern, comprising the steps of:
forming an etch stop film and an interlayer dielectric film comprising an SiOC:H group material on a substrate having an electrical connection layer formed thereon;
forming an anti-reflection layer on the interlayer dielectric film;
forming a primary opening by etching the anti-reflection layer and the interlayer dielectric film to expose a surface of the etch stop film;
forming a sacrificial film comprising a low dielectric constant material in the primary opening and on the anti-reflection layer;
plasma-processing the sacrificial film to densify the sacrificial film;
forming a trench photoresist pattern having a width larger than that of the primary opening on the sacrificial film after plasma-processing the sacrificial film;
sequentially etching the sacrificial film, the anti-reflection layer and the interlayer dielectric film using the trench photoresist pattern as an etch mask so as to form a secondary opening of a trench shape, and removing the trench photoresist pattern, said secondary opening extending from an upper portion of the primary opening; and
removing the sacrificial film remaining, removing the exposed etch stop film and anti-reflection layer, and filling the primary and secondary openings with metal so as to be electrically coupled with the electrical connection layer.
2. The method of claim 1, wherein said step of removing the sacrificial film is performed by a dry etch back process.
3. The method of claim 1, wherein said electrical connection layer comprises copper.
4. The method of claim 1, wherein said sacrificial film comprises hydrogen silsesquioxane(HSQ).
5. The method of claim 1, wherein said sacrificial film comprises methyl silsesquioxane(MSQ) MSQ.
6. The method of claim 1, wherein said sacrificial film comprises benzocyclobutene.
7. The method of claim 1, wherein plasma-processing said sacrificial film is performed by using, as plasma source gas, a mixed gas comprising at least one of oxygen, nitrogen, ammonia, helium and hydrogen.
8. The method of claim 1, wherein said etch stop film comprises SiC or SiN.
9. The method of claim 1, wherein said anti-reflection layer comprises SiC or SiON.
10. A method of forming a dual damascene wiring pattern, comprising the steps of:
forming an etch stop film and an interlayer dielectric film comprising an SiOC:H group material on a substrate having an electrical connection layer formed thereon;
forming an anti-reflection layer on the interlayer dielectric film;
forming a primary opening by etching the anti-reflection layer and the interlayer dielectric film to expose a surface of the etch stop film;
forming a sacrificial film comprising a low dielectric constant material in the primary opening and on the anti-reflection layer;
forming a capping thin film on a portion of the sacrificial film that is over the anti-reflection layer, and forming a trench photoresist pattern having a width larger than that of the primary opening on the capping thin film;
sequentially etching the capping thin film, the sacrificial film, the anti-reflection layer and the interlayer dielectric film using the trench photoresist pattern as an etch mask so as to form a secondary opening of a trench shape, and removing the trench photoresist pattern, said secondary opening extending from an upper portion of the primary opening; and
removing the remaining capping thin film and the remaining sacrificial film, removing the exposed etch stop film and anti-reflection layer, and filling the primary and secondary openings with metal so as to be electrically coupled with the electrical connection layer.
11. The method of claim 10, wherein the step of removing the sacrificial film is performed by a dry or wet etch back process.
12. The method of claim 10, wherein said capping thin film comprises an oxide film or an inorganic reflection preventing film.
13. The method of claim 10, wherein the sacrificial film comprises hydrogen silsesquioxane(HSQ).
14. A method of forming a dual damascene wiring pattern, comprising the steps of:
forming an etch stop film and an interlayer dielectric film comprising an SiOC:H group material on a substrate having an electrical connection layer formed thereon;
forming an anti-reflection layer on the interlayer dielectric film;
forming a primary opening by etching the anti-reflection layer and the interlayer dielectric film to expose a surface of the etch stop film;
forming a sacrificial film comprising a low dielectric constant material in the primary opening and on the anti-reflection layer;
forming an anti-reflection coating film on a portion of the sacrificial film that is over the anti-reflection layer, and forming a trench photoresist pattern having a width larger than that of the primary opening on the anti-reflection coating film;
sequentially etching the anti-reflection coating film, the sacrificial film, the anti-reflection layer and the interlayer dielectric film using the trench photoresist pattern as an etch mask so as to form a secondary opening of a trench shape, and removing the trench photoresist pattern, said secondary opening extending from an upper portion of the primary opening; and
removing the remaining anti-reflection coating film and the remaining sacrificial film, removing the exposed etch stop film and anti-reflection layer, and filling the primary and secondary openings with metal so as to be electrically coupled with the electrical connection layer.
15. The method of claim 14, wherein said step of removing the sacrificial film is performed by a dry or wet etch back process.
16. The method of claim 14, wherein said electrical connection layer comprises copper.
17. The method of claim 14, wherein said sacrificial film comprises hydrogen silsesquioxane(HSQ).
18. The method of claim 14, wherein said anti-reflection coating film comprises an organic coating thin film.