What is claimed is:
1. A method for making a metallization structure for a semiconductor device, comprising:
forming a substantially planar first dielectric layer on a substrate;
forming at least one metal layer over the first dielectric layer;
forming a conducting layer over the metal layer;
forming a second dielectric layer over the conducting layer;
removing aligned portions of the second dielectric layer, conducting layer, and metal layer to form a multi-layer structure; and
forming metal spacers on sidewalls of the multi-layer structure.
2. The method of claim 1, wherein forming the first dielectric layer comprises forming a silicon oxide or BPSG layer.
3. The method of claim 2, further including forming the at least one metal layer of Ti, Ta, W, Co or Mo or an alloy or a compound of any thereof, including TaN or TiN.
4. The method of claim 3, further including forming a second metal layer between the first metal layer and the substrate and comprising TiN, TiW, WN, or TaN.
5. The method of claim 1, further including forming the at least one metal layer of titanium or titanium nitride.
6. The method of claim 1, wherein the at least one metal layer is a single metal layer and further comprising forming the single metal layer of titanium or titanium nitride.
7. The method of claim 1, further comprising forming the conducting layer from the group comprising aluminum and copper.
8. The method of claim 7, further including forming the conducting layer of an aluminum-copper alloy.
9. The method of claim 1, further including forming the metal spacers of at least one layer of Ti, Ta, W, Co or Mo, or alloys thereof or compounds thereof, including TaN and TiN.
10. The method of claim 9, further including forming the metal spacers of titanium or titanium nitride.
11. The method of claim 1, further comprising forming a dielectric layer on the conducting layer to have sidewalls aligned with the conductive layer sidewalls, and forming the metal spacers to extend along the sidewalls of the dielectric layer.
12. The method of claim 11, further comprising forming the dielectric layer of a low dielectric constant material.
13. The method of claim 12, further comprising forming the dielectric layer of a fluorine-doped silicon oxide.
14. The method of claim 1, further comprising forming the at least one metal layer and the metal spacers of the same metal.
15. The method of claim 1, further comprising forming the at least one metal layer by vapor deposition.
16. The method of claim 14, further comprising forming the at least one metal layer by CVD, PVD or PECVD.
17. The method of claim 1, further comprising forming the conducting layer by vapor deposition.
18. The method of claim 17, further comprising forming the conducting layer by CVD, PVD or PECVD.
19. The method of claim 1, further comprising forming the metal spacers by vapor deposition and directional etching.
20. The method of claim 19, further comprising effecting the vapor deposition as CVD, PVD or PECVD.
21. The method of claim 1, wherein removing aligned portions of the second dielectric layer, conducting layer, and metal layer to form a multi-layer structure is effected by patterning and etching the second dielectric layer, the conducting layer, and the metal layer.
22. The method of claim 1, further comprising forming the metal spacers by forming a metal spacer layer over the multi-layer structure and first dielectric layer and removing portions thereof overlying the first and second dielectric layers.
23. The method of claim 22, further comprising forming the metal spacer layer over the multi-layer structure and first dielectric layer by a conformal deposition process.
24. The method of claim 23, wherein the portions of the metal layer over the multi-layer structure and first dielectric layer are removed by etching.
25. The method of claim 1, further comprising:
removing any remaining portion of the second dielectric layer and upper portions of the metal spacers laterally adjacent thereto.
26. The method of claim 25, further comprising removing any remaining portion of the second dielectric layer and upper portions of the metal spaces by etching.
27. A method for making a metallization structure comprising:
forming a substrate comprising at least one metal layer on the surface thereof;
forming a dielectric layer over at least one the metal layer;
forming an aperture having at least one sidewall through the dielectric layer to expose a surface of the at least one metal layer;
forming a metal spacer on the at least one sidewall of the aperture; and
forming a conductive layer in a remaining portion of the aperture.
28. The method of claim 27, further comprising forming the dielectric layer of silicon oxide.
29. The method of claim 27, further including forming the at least one metal layer of Ti, Ta, W, Co or Mo or alloys or compounds thereof, including TaN or TiN.
30. The method of claim 29, wherein the at least one metal layer comprises a first metal layer, and further including forming a second metal layer between the first metal layer and the substrate and comprising TiN, TiW, WN, or TaN.
31. The method of claim 27, further including forming the at least one metal layer of titanium or titanium nitride.
32. The method of claim 27, further comprising forming the at least one metal layer by vapor deposition.
33. The method of claim 32, further comprising forming the at least one metal layer by CVD, PVD or PECVD.
34. The method of claim 27, further comprising forming the conducting layer by vapor deposition.
35. The method of claim 34, further comprising forming the conducting layer by CVD, PVD or PECVD.
36. The method of claim 27, further comprising forming the at least one metal layer and the metal spacer of the same metal.
37. The method of claim 27, further comprising forming the metal spacer by vapor deposition and directional etching.
38. The method of claim 27, further including forming the metal spacer of at least one layer of Ti, Ta, W, Co or Mo, or alloys or compounds thereof, including TaN or TiN.
39. The method of claim 3 8, further including forming the metal spacer of titanium or titanium nitride.
40. The method of claim 27, further comprising forming at least one upper metal layer on the conductive layer.
41. The method of claim 40, further comprising forming the at least one upper metal layer on the conductive layer from Ti, Ta, W, Co or Mo or alloys or compounds thereof, including TaN or TiN.
42. The method of claim 40, further comprising forming the at least one upper metal layer as a plurality of upper metal layers.
43. The method of claim 40, further comprising forming the at least one upper metal layer of titanium or titanium nitride.
44. The method of claim 40, further comprising forming the at least one upper metal layer by vapor deposition.
45. The method of claim 44, wherein the vapor deposition is effected by CVD, PVD or PECVD.
46. The method of claim 27, further comprising removing the dielectric layer and portions of the at least one metal layer not underlying the aperture.
47. The method of claim 46, further comprising removing the dielectric layer by using a hydrofluoric acid wet etch solution or an oxide dry etch process.
48. The method of claim 46, further comprising removing the portions of the at least one metal layer by directional etching.
49. A method for making a metallization structure comprising:
forming a substrate comprising at least one metal layer on the surface thereof;
forming a dielectric layer over the at least one metal layer;
forming an aperture through the dielectric layer to expose a surface of the at least one metal layer;
forming a conducting layer in the aperture;
forming at least one upper metal layer overlying the dielectric layer and the conducting layer in the aperture;
removing portions of the at least one upper metal layer overlying the dielectric layer, removing the dielectric layer, and removing portions of the at least one metal layer surrounding the conducting layer to form a multi-layer metal structure having at least one sidewall; and
forming a metal spacer on the at least one sidewall of the multi-layer metal structure.
50. The method of claim 49, further comprising forming the dielectric layer of silicon oxide.
51. The method of claim 49, further including forming the at least one metal layer of Ti, Ta, W, Co or Mo or alloys or compounds thereof, including TaN or TiN.
52. The method of claim 51, wherein the at least one metal layer comprises a first metal layer, and further including forming a second metal layer between the first metal layer and the substrate and comprising TiN, TiW, WN, or TaN.
53. The method of claim 49, further including forming the at least one metal layer of titanium or titanium nitride.
54. The method of claim 49, further comprising forming the at least one metal layer by vapor deposition.
55. The method of claim 54, further comprising forming the at least one metal layer by CVD, PVD or PECVD.
56. The method of claim 49, further comprising forming the conducting layer by vapor deposition.
57. The method of claim 56, further comprising forming the conducting layer by CVD, PVD or PECVD.
58. The method of claim 49, further comprising forming the at least one metal layer and the metal spacer of the same metal.
59. The method of claim 49, further comprising forming the metal spacer by vapor deposition of a metal layer over the multi-layer metal structure and directional etching of the vapor-deposited metal layer.
60. The method of claim 49, further including forming the metal spacer of at least one layer of Ti, Ta, W, Co or Mo, or alloys thereof or compounds thereof, including TaN or TiN.
61. The method of claim 60, further including forming the metal spacer of titanium or titanium nitride.
62. The method of claim 49, further comprising forming the at least one upper metal layer on the conducting layer from Ti, Ta, W, Co or Mo or an alloy or a compound of any thereof, including TaN or TiN.
63. The method of claim 62, further comprising forming the at least one upper metal layer as a plurality of upper metal layers.
64. The method of claim 49, further comprising forming the at least one upper metal layer of titanium or titanium nitride.
65. The method of claim 49, further comprising forming the at least one upper metal layer by vapor deposition .
66. The method of claim 65, where in the vapor deposition is effected by CVD, PVD or PECVD.
67. The method of claim 49, further comprising removing the dielectric layer by using a hydrofluoric acid wet etch solution or an oxide dry etch process.
68. The method of claim 49, further comprising removing the portions of the at least one metal layer by directional etching.
69. The method of claim 49, further comprising forming the conducting layer from at least one of aluminum and copper.
70. The method of claim 49, comprising forming the metal layer, metal spacer, and upper metal layer of the same metal.
71. The method of claim 70, wherein the metal is Ti.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for monitoring a load driven by a power semiconductor switch, comprising:
driving a control electrode of the power semiconductor switch, in such a way that a rise in a load current through the power semiconductor switch is effected after a delay time;
generating a diagnostic current flowing through the load, wherein the diagnostic current brings about a voltage drop across the load before the delay time has elapsed; and
evaluating the voltage drop across the load before the delay time has elapsed.
2. The method as claimed in claim 1, wherein evaluating the voltage drop comprises:
comparing the voltage drop across the load with a first threshold value before the delay time has elapsed.
3. The method as claimed in claim 2, wherein evaluating the voltage drop further comprises:
comparing the voltage drop across the load with a second threshold value before the delay time has elapsed.
4. The method as claimed in claim 2, wherein evaluating the voltage drop further comprises:
generating a signal responsive to the voltage drop across the load not exceeding the first threshold value.
5. The method as claimed in claim 3, wherein evaluating the voltage drop (Vout) further comprises:
generating a signal responsive to the voltage drop across the load exceeding the second threshold value.
6. (canceled)
7. The method as claimed in claim 1, wherein the diagnostic current is smaller than a nominal value of the load current.
8. The method as claimed in claim 1, further comprising:
responsive to the voltage drop being evaluated as excessively low, switching the power semiconductor switch off.
9. A circuit arrangement for driving a power semiconductor switch, comprising:
a power semiconductor switch connected to a load and having a load path connected in series with the load, and further having a control electrode;
a driver circuit, connected to the control electrode and configured to drive the control electrode depending on a control signal in such a way that a delay time elapses between the application of a driver signal to the control electrode and a rise in a load current through the load path of the power semiconductor switch; and
a monitoring circuit, configured to generate a diagnostic current through the load and evaluate a voltage drop across the load before the delay time has elapsed.
10. The circuit arrangement as claimed in claim 9, wherein the monitoring circuit comprises:
a current source configured to selectively generate the diagnostic current in response to a control input.
11. The circuit arrangement as claimed in claim 9, wherein the monitoring circuit comprises:
a transistor, having a load path connected in series with the load and configured such that the diagnostic current flows through the load path of the transistor.
12. The circuit arrangement as claimed in claim 11, wherein the power semiconductor switch and the transistor are formed in a same cell array.
13. The circuit arrangement as claimed in claim 9, wherein the monitoring circuit comprises:
a first comparator configured to compare the voltage drop across the load with a first threshold value, the first comparator having an output at which a result of the comparison with the first threshold value is available.
14. The circuit arrangement as claimed in claim 13, in which the monitoring circuit furthermore comprises:
a second comparator configured to compare the voltage drop across the load with a second threshold value, the second comparator having an output at which a result of the comparison with the second threshold value is available.
15. The circuit arrangement as claimed in claim 14, further comprising a logic circuit configured to receive the outputs of the comparators and to generate a signal based on the comparison results of the first and second comparators.
16. (canceled)
17. The circuit arrangement as claimed in claim 9, further comprising:
a drive logic circuit configured to receive the control signal and to activate and deactivate the driver circuit depending on the control signal.
18. The circuit arrangement as claimed in claim 9, wherein the power semiconductor switch is one of a metal-oxide semiconductor field-effect transistor (MOSFET) and an insulated-gate bipolar transistor (IGBT).
19. The circuit arrangement as claimed in claim 9, wherein the power semiconductor switch is configured in the circuit arrangement as a low-side switch.
20. The circuit arrangement as claimed in claim 9, wherein the power semiconductor switch is configured in the circuit arrangement as a high-side switch.
21. The method of claim 8, wherein switching off the power semiconductor is performed prior to the load current reaching a nominal value that would otherwise be reached if the load current were not excessively low.
22. The circuit arrangement of claim 11, wherein the transistor has a control electrode having a lower capacitance than the control electrode of the power semiconductor switch.
23. An apparatus configured to drive a power semiconductor switch having a load path in series with a load, the apparatus comprising:
a first circuit configured to generate a voltage rise in a first signal at a control electrode of the power semiconductor switch, the voltage rise causing the load path of the power semiconductor switch to conduct after a delay from a beginning of the voltage rise; and
a second circuit configured to generate a diagnostic current through the load and to evaluate a voltage drop across the load that occurs at a time prior to the delay expiring.
24. The apparatus of claim 23, wherein the diagnostic current is 10 mA or less.
25. The apparatus of claim 23, wherein the second circuit is further configured to cause the first signal to drop in voltage responsive to the evaluated voltage drop being less than a threshold value.