1. A method for driving at least a portion of a passive matrix display system having rows and columns forming pixels, comprising steps of:
(a) initially driving the portion of the passive matrix display system to a uniform state;
(b) outputting to the columns a column voltage signal, cycling through four non-negative voltage levels, wherein the first voltage level is sufficiently high to change the pixel state to a planar reflective state, the second voltage will put the pixel into a weakly scattering focal conic state, the third voltage is sufficiently low that it cannot substantially change the pixel state, and the fourth voltage is the difference between the first voltage and the second voltage, and wherein a time period for the first and third voltages is proportional to t1 and a time period for the second and fourth voltages is proportional to t2, wherein
t
\u2062
\u2062
1
=
n
\xd7
driveperiod
2
\u2062
(
N
–
1
)
t
\u2062
\u2062
2
=
(
N
–
1
–
n
)
\u2062
(
driveperiod
)
2
\u2062
(
N
–
1
)
wherein N is a total number of desired levels of gray scale;
n is a number representing a particular desired level of gray scale within the range of 0 to N\u22121; and
drive period is a length of time inversely proportional to a frequency of oscillation of the row voltages;
(c) outputting to the rows a first row voltage signal oscillating between a non-planar voltage and a planar voltage, wherein the first row voltage signal is applied to a row of the matrix being written; and
(d) outputting to the rows a second row voltage signal oscillating between a first voltage and a second voltage, wherein the difference between the second row voltage signal and column voltage signal at any time is sufficiently low that a state of a pixel receiving the second row voltage signal and the column voltage signal will remain substantially unchanged, and wherein the second row voltage signal is applied to all rows of the matrix not being written.
2. The method of claim 1 wherein N=32.
3. The method of claim 1 wherein the first row voltage signal, the second row voltage signal and the column voltage signal oscillate at a frequency within the range of 50 Hz to 500 Hz.
4. The method of claim 3 wherein each row is written over a length 1, 2, 3, or 4 periods, wherein the period is inversely related to the frequency.
5. A system for driving a display having rows and columns forming pixels comprising:
(a) a passive matrix display having rows and columns forming pixels;
(b) a column driver outputting to the columns a column voltage signal, cycling through four non-negative voltage levels, wherein the first voltage level is sufficiently high to change the pixel state to a planar reflective state, the second voltage will put the pixel into a weakly scattering focal conic state, the third voltage is sufficiently low that it cannot substantially change the pixel state, and the fourth voltage is the difference between the first voltage and the second voltage, and wherein a time period for the first and third voltages is proportional to t1 and a time period for the second and fourth voltages is proportional to t2, wherein
t
\u2062
\u2062
1
=
n
\xd7
driveperiod
2
\u2062
(
N
–
1
)
t
\u2062
\u2062
2
=
(
N
–
1
–
n
)
\u2062
(
driveperiod
)
2
\u2062
(
N
–
1
)
wherein N is the total number of desired levels of gray scale;
n is a number representing a particular desired level of gray scale within the range of 0 to N\u22121; and
drive period is a length of time inversely proportional to a frequency of oscillation of the row voltages;
(c) a row driver outputting to the rows a first row voltage signal and a second row voltage signal, wherein the first row voltage signal oscillates between a non-planar voltage and a planar voltage, and is applied to a row of the matrix being written; and the second row voltage signal oscillates between a first voltage and a second voltage, the difference between the second row voltage signal and column voltage signal at any time being sufficiently low that a state of a pixel receiving the second row voltage signal and the column voltage signal will remain substantially unchanged, and is applied to all of the rows of the matrix not being written; and
(d) a controller electrically coupled to the passive matrix display, the row driver, and the column driver, wherein the controller controls the first row voltage signal, the second row voltage signal, and the column voltage signal.
6. The system of claim 5 wherein the passive matrix display comprises a cholesteric liquid crystal display.
7. The system of claim 5 wherein the cholesteric liquid crystal display comprises a plurality of active layers and each of the active layers is driven independently.
8. The method of claim 5 wherein the first row voltage signal, the second row voltage signal, and the column voltage signal oscillate at a frequency within the range of 50 Hz to 500 Hz.
9. The method of claim 8 wherein each row is written over a length 1, 2, 3, or 4 periods, and the period is inversely related to the frequency.
10. The method of claim 4 wherein N=32.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for producing a capacitive micro-machined ultrasonic transducer (cMUT), comprising:
a. providing a cMUT structure, wherein the cMUT structure defines one or more cMUT elements that include: (i) a substrate layer, (ii) an electrode plate, (iii) a membrane layer, and (iv) an electrode ring;
b. defining at least one hole through the membrane layer for each cMUT element;
c. applying a bias voltage across the membrane and substrate layers of the one or more cMUT elements so as to collapse the membrane layer relative to the substrate layer; and
d. fixing and sealing the collapsed membrane layer relative to the substrate layer by applying an encasing layer.
2. The method according to claim 1, further comprising: (i) discontinuing the bias voltage, or (ii) reducing the bias voltage to an operating voltage.
3. The method according to claim 1, wherein the bias voltage is a well-defined DC voltage supplied by a battery.
4. The method according to claim 3, wherein the well-defined DC voltage falls between 10 and 250V.
5. The method according to claim 1, wherein the bias voltage is effective to regulate the amount of collapse.
6. The method according to claim 5, wherein the regulation of the amount of collapse is effective to optimize performance.
7. The method according to claim 1, wherein the at least one hole is between about 1 and 25 microns in diameter.
8. The method according to claim 1, wherein the at least one hole is defined using an optical lithography technique selected from the group consisting of g-line lithography, i-line lithography, nano-imprint lithography and e-beam lithography.
9. The method according to claim 1, wherein the electrode plate is a circular electrode plate fabricated from a metallic or non-metallic conductive material.
10. The method according to claim 9, wherein an outer diameter of the electrode ring is configured and dimensioned to substantially match a diameter of the circular electrode plate and wherein a center of electrode the ring and a center of the circular electrode plate are substantially aligned.
11. The method according to claim 1, wherein the substrate layer comprises silicon.
12. The method according to claim 1, wherein the membrane layer comprises a CMOS compatible material comprising one of silicon nitride, an oxide, tetra ethyl oxysilane (TEOS), or poly-silicon.
13. The method according to claim 1, wherein the encasing layer comprises a CMOS compatible material comprising one of silicon nitride, an oxide, tetra ethyl oxysilane (TEOS), or poly-silicon.
14. The method according to claim 1, wherein the electrode plate is a metallic or non-metallic conductive material.
15. The method according to claim 1, wherein the cMUT is fabricated, at least in part, using plasma-enhanced chemical vapor deposition (PECVD) andor low pressure chemical vapor deposition (LPCVD).
16. The method according to claim 1, wherein the electrode plate of the cMUT element is fixed relative to a top surface of the substrate layer.
17. The method according to claim 1, wherein the membrane of the cMUT element is fixed relative to a top face of the substrate layer so as to define a cavity between the membrane and the substrate layer.
18. The method according to claim 1, wherein the electrode ring is fixed relative to a top surface of the membrane layer.
19. The method according to claim 1, wherein the at least one hole is defined through the membrane layer relative to a center of the electrode ring.
20. The method according to claim 1, wherein a diameter of the at least one hole is less than an inner diameter of the electrode ring.
21. The method according to claim 1, wherein an area of collapse of the membrane layer is proximate to the hole.
22. The method according to claim 1, wherein the bias voltage is: (i) maintained throughout the fixing and sealing process, (ii) reduced prior to the fixing and sealing process, (iii) reduced during the fixing and sealing process; or (iv) a combination thereof.