1. An SMT LED device, comprising:
an LED comprising two solder slugs at a bottom of the LED;
a circuit board supporting the LED thereon; and
a pair of first solder pads formed on the circuit board and spaced from each other;
wherein a positioning hole is formed in each of the pair of first solder pads corresponding to a position of each of the two solder slugs, each of the two solder slugs being received in the positioning hole; and
wherein a pair of second solder pads are formed on and are in direct physical contact with the circuit board, each of the pair of second solder pads is positioned in a bottom of the positioning hole and apart from the corresponding first solder pad in a horizontal direction, a height of each of the pair of second solder pads is smaller than a height of each of the pair of first solder pads, and each of the two solder slugs is electrically connected to a corresponding one of the pair of second solder pads.
2. The SMT LED device of claim 1, wherein the LED further comprises a substrate, a pair of electrodes formed on the substrate and extending from a top surface of the substrate to a bottom surface of the substrate, an LED die arranged over the substrate and electrically connected to each of the pair of electrodes, the two solder slugs each extending downward from a lateral periphery of a bottom face of a corresponding one of the pair of electrodes.
3. The SMT LED device of claim 1, wherein the pair of first solder pads physically contact the circuit board.
4. The SMT LED device of claim 1, wherein the pair of first solder pads and the pair of second solder pads are on a same plane defined by the circuit board.
5. The SMT LED device of claim 1, wherein each of the two solder slugs is apart from the corresponding one of the pair of first solder pads, and a distance between each of the two solder slugs and the inner sidewall of the corresponding one of the pair of first solder pads is less than 10 microns.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A random number generator circuit comprising:
a physical random number generating element generating and outputting physical random numbers;
a digitizing circuit digitizing the physical random numbers and outputting a random number sequence;
a testing circuit testing the random number sequence; and
an error correcting code circuit including: a shift register having the random number sequence input thereto; a multiplier multiplying the random number sequence stored in the shift register by an error-correcting-code generating matrix; and a selector switch selecting and outputting one of an output of the shift register and an output of the multiplier in accordance with a result of a test conducted by the testing circuit, the error correcting code circuit outputting the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection,
the testing circuit testing the corrected random number sequence when the result of the test indicates a rejection.
2. The circuit according to claim 1, wherein
the register and the multiplier constitute a linear feedback shift register, and
the error correcting code circuit is placed between the digitizing circuit and the testing circuit, and sends the output of the digitizing circuit to the testing circuit until the result of the test conducted by the testing circuit indicates a rejection.
3. The circuit according to claim 2, further comprising
a memory storing information about a coefficient of each order of a generator polynomial of the error-correcting-code generating matrix,
wherein the multiplier includes pass transistors corresponding to the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, the pass transistors being switched on and off based on the information stored in the memory.
4. The circuit according to claim 1, further comprising
an XOR gate performing an exclusive-OR operation on the output of the digitizing circuit and the output of the error correcting code circuit,
wherein
the shift register and the multiplier constitute a linear feedback shift register, and
the testing circuit tests a random number sequence that is output from the XOR gate.
5. The circuit according to claim 4, further comprising
a memory storing information about a coefficient of each order of a generator polynomial of the error-correcting-code generating matrix,
wherein the multiplier includes pass transistors corresponding to the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, the pass transistors being switched on and off based on the information stored in the memory.
6. The circuit according to claim 1, further comprising a memory,
wherein the error correcting code circuit is included in the memory.
7. The circuit according to claim 1, wherein
the error correcting code circuit includes:
a first XOR gate including an input terminal to receive one of digital random numbers that are sent as input signals;
a shift register including a plurality of flip-flops connected in series;
a plurality of pass transistors corresponding to the respective flip-flops, one terminal of each of the pass transistors being connected to an output terminal of each corresponding one of the flip-flops, a gate of each of the pass transistors receiving a signal in accordance with a coefficient of a generator polynomial of the error-correcting-code generating matrix;
a second XOR gate performing an exclusive-OR operation on signals that are send from the respective other terminals of the pass transistors;
a switch being switched on and off in accordance with the result of a test conducted by the testing circuit, and sending an output of the second XOR gate to the other input terminal of the first XOR gate; and
a selector switch selecting and outputting one of an output of the flip-flop in the last stage of the shift register and the output of the second XOR gate, in accordance with the result of the test conducted by the testing circuit.
8. The circuit according to claim 1, wherein
the error correcting code circuit includes:
a shift register including a plurality of flip-flops connected in series;
a first XOR gate provided on an input terminal of the flip-flop in the input stage of the shift register;
a plurality of second XOR gates provided between the respective adjacent flip-flops;
a third XOR gate provided on an output side of the flip-flop in the last stage of the shift register;
a plurality of pass transistors corresponding to the respective first through third XOR gates, one terminal of each of the pass transistors being connected to an input terminal of each corresponding one of the XOR gates, the other terminals of the pass transistors being connected together, a gate of each of the pass transistors receiving a signal in accordance with a coefficient of a generator polynomial of the error-correcting-code generating matrix;
a first selector switch circuit selectively sending an input signal to the other terminal of each of the pass transistors or to the other input terminal of the first XOR gate, in accordance with the result of the test conducted by the testing circuit; and
a second selector switch circuit selectively sending one of a signal at the other terminal of each of the pass transistors and an output of the third XOR gate, in accordance with the result of the test conducted by the testing circuit.
9. A cryptographic circuit comprising:
the random number generator circuit according to claim 1;
a first memory storing personal information; and
a CPU,
wherein, when the cryptographic circuit is connected to a system for personal verification, the CPU causes the error correcting code circuit to multiply the random number sequence by an error-correcting-code generating matrix, to change random number quality.
10. The circuit according to claim 9, wherein
the register and the multiplier constitute a linear feedback shift register, and
the error correcting code circuit is placed between the digitizing circuit and the testing circuit, and sends the output of the digitizing circuit to the testing circuit until the result of the test conducted by the testing circuit indicates a rejection.
11. The circuit according to claim 10, further comprising
a second memory storing information about a coefficient of each order of a generator polynomial of the error-correcting-code generating matrix,
wherein the multiplier includes pass transistors corresponding to the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, the pass transistors being switched on and off based on the information stored in the second memory.
12. The circuit according to claim 9, further comprising
an XOR gate performing an exclusive-OR operation on the output of the digitizing circuit and the output of the error correcting code circuit,
wherein
the shift register and the multiplier constitute a linear feedback shift register, and
the testing circuit tests a random number sequence that is output from the XOR gate.
13. The circuit according to claim 12, further comprising
a second memory storing information about a coefficient of each order of a generator polynomial of the error-correcting-code generating matrix,
wherein the multiplier includes pass transistors corresponding to the coefficients of the respective orders of the generator polynomial of the error-correcting-code generating matrix, the pass transistors being switched on and off based on the information stored in the second memory.
14. The circuit according to claim 9, further comprising a second memory,
wherein the error correcting code circuit is included in the second memory.
15. The circuit according to claim 9, wherein
the error correcting code circuit includes:
a first XOR gate including an input terminal to receive one of digital random numbers that are sent as input signals;
a shift register including a plurality of flip-flops connected in series;
a plurality of pass transistors corresponding to the respective flip-flops, one terminal of each of the pass transistors being connected to an output terminal of each corresponding one of the flip-flops, a gate of each of the pass transistors receiving a signal in accordance with a coefficient of a generator polynomial of the error-correcting-code generating matrix;
a second XOR gate performing an exclusive-OR operation on signals that are send from the respective other terminals of the pass transistors;
a switch being switched on and off in accordance with the result of the test conducted by the testing circuit, and sending an output of the second XOR gate to the other input terminal of the first XOR gate; and
a selector switch selecting and outputting one of an output of the flip-flop in the last stage of the shift register and the output of the second XOR gate, in accordance with the result of the test conducted by the testing circuit.
16. The circuit according to claim 9, wherein
the error correcting code circuit includes:
a shift register including a plurality of flip-flops connected in series;
a first XOR gate provided on an input terminal of the flip-flop in the input stage of the shift register;
a plurality of second XOR gates provided between the respective adjacent flip-flops;
a third XOR gate provided on an output side of the flip-flop in the last stage of the shift register;
a plurality of pass transistors corresponding to the respective first through third XOR gates, one terminal of each of the pass transistors being connected to an input terminal of each corresponding one of the XOR gates, the other terminals of the pass transistors being connected together, a gate of each of the pass transistors receiving a signal in accordance with a coefficient of a generator polynomial of the error-correcting-code generating matrix;
a first selector switch circuit selectively sending an input signal to the other terminal of each of the pass transistors or to the other input terminal of the first XOR gate, in accordance with the result of the test conducted by the testing circuit; and
a second selector switch circuit selectively sending one of a signal at the other terminal of each of the pass transistors and an output of the third XOR gate, in accordance with the result of the test conducted by the testing circuit.