What is claimed is:
1. A method for discharging a word line, the method comprising:
discharging the word line to a first power supply through a first switch that is connected to the word line until the first switch reaches a threshold voltage, and simultaneously, discharging the word line to a second power supply through a second switch that is connected to the word line; and
discharging the word line to the second power supply through the second switch after the first switch reaches the threshold voltage.
2. The method of claim 1, wherein the first switch is a first transistor having a first threshold voltage, and the second switch is a second transistor having a second threshold voltage, and the second threshold voltage is higher than the first threshold voltage.
3. The method of claim 1, wherein the word line includes a sub word line select signal line.
4. The method of claim 1, wherein the first power supply is ground power supply, and the second power supply is a negative power supply.
5. A method for discharging a word line, the method comprising:
discharging the word line to a first power supply through a first switch that is turned on in response to the voltage of the word line, and simultaneously, discharging the word line to a second power supply through a second switch that is connected to the word line; and
discharging the word line to the second power supply through the second switch after the first switch is turned off in response to a reduction in voltage on the word line.
6. The method of claim 5, wherein the first switch is a first transistor having a first threshold voltage, and the second switch is a second transistor having a second threshold voltage, and the second threshold voltage is higher than the first threshold voltage.
7. The method of claim 5, wherein the word line includes a sub word line select signal line.
8. A method for discharging a word line, the method comprising:
discharging the word line to a first power supply through a first current path that is formed in response to a predetermined word line select signal and the voltage of the word line, and simultaneously, discharging the word line to a second power supply through a second current path that is formed in response to the word line select signal; and
discharging the word line to the second power supply through the second current path when the first current path is blocked in response to a reduction voltage on the word line.
9. The method of claim 8, wherein the first current path is formed using a first transistor having a predetermined threshold voltage.
10. The method of claim 9, wherein the second current path is formed using a second transistor having a predetermined threshold voltage, and the threshold voltage of the second transistor is higher than that of the first transistor.
11. The method of claim 8, wherein the first power supply is ground power supply, and the second power supply is a negative power supply.
12. A semiconductor memory device comprising:
a word line;
a first switch that is connected between the word line and a first power supply and discharges the word line to the first power supply in response to a word line select signal and the voltage of the word line; and
a second switch that is connected between the word line and a second power supply and discharges the word line to the second power supply in response to the word line select signal.
13. The device of claim 12, wherein the first power supply is ground power supply, and the second power supply is a negative power supply.
14. The device of claim 12, wherein the first switch is a first transistor having a first threshold voltage, and the second switch is a second transistor having a second threshold voltage, and the second threshold voltage is higher than the first threshold voltage.
15. A semiconductor memory device comprising:
a word line;
a transistor that is connected between the word line and a first power supply and discharges the word line to the first power supply in response to a word line select signal and the voltage of the word line; and
a second switch that is connected between the word line and a second power supply and discharges the word line to the second power supply in response to the word line select signal.
16. The device of claim 15, wherein the first power supply is ground power supply, and the second power supply is a negative power supply.
17. A semiconductor memory device comprising:
a word line;
a first pull-up circuit for pulling up the word line to the level of a boosting voltage in response to a first logic level of a word line select signal;
a first node;
a switch for connecting the first node to the word line in response to a second logic level of the word line select signal;
a first pull-down circuit for pulling down the word line towards the level of a ground voltage in response to the voltage of the first node; and
a second pull-down circuit for pulling down the word line to the level of a negative voltage in response to the second logic level of the word line select signal;
wherein the first pull-down circuit is deactivated when the voltage of the first node becomes lower than a predetermined voltage.
18. A semiconductor memory device comprising:
a word line;
a first pull-down circuit to discharge the word line to a first power supply in response to a word line select signal, the first pull-down circuit having the capability to turn itself off when the voltage on the word line reaches a first voltage level; and
a second pull-down circuit to discharge the word line to a second power supply, with a voltage level lower than that of the first power supply, in response to the word line select signal.
19. The device of claim 18, wherein the first power supply is a ground reference and the second power supply is a negative voltage generator located on the device.
20. The device of claim 19, the first pull-down circuit comprising:
a first transistor connected between the word line and the ground reference, and controlled by the voltage at the first node; a second transistor connected between the first node and the ground reference; and
a third transistor connected between the word line and the first node; wherein the second transistor is activated when the word line select signal is asserted, and the third transistor is activated when the word line select signal is asserted.
21. The device of claim 20, wherein during discharge the word line connects to the first and third transistors through a sub word line select signal line, the first pull-down circuit also serving to discharge the sub word line select signal line.
22. The device of claim 20, wherein the first transistor, when on, has the ability to draw substantially more current from the word line than the second pull-down circuit can draw.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A module, comprising:
a lead assembly having first and second opposed surfaces, each extending in a first direction and a second direction transverse to the first direction, and a plurality of exposed module contacts adjacent an edge of at least one of the first and second surfaces configured to mate with corresponding contacts of a socket, the lead assembly including first and second gaps extending between the first and second surfaces;
first and second microelectronic elements having front surfaces facing the first surface of the lead assembly, each microelectronic element having chip contacts electrically connected to the lead assembly, the front surface of the second microelectronic element partially overlying a rear surface of the first microelectronic element and attached thereto, the first microelectronic element having a lateral edge extending between the front and rear surfaces thereof and extending in the second direction, the front surface of the second microelectronic element projecting in the first direction beyond the lateral edge,
the second microelectronic element having first and second opposed edges extending between the front and rear surfaces of the second microelectronic element and extending in the second direction, the front surface of the second microelectronic element having a first outer region adjacent the first edge, a second outer region adjacent the second edge, and a central region disposed between the first and second outer regions, each of the first and second outer regions and the central region having equal width such that the central region extends a middle third of a distance between the first and second edges, the chip contacts of the second microelectronic element disposed in the central region beyond the lateral edge of the first microelectronic element;
first wire bonds extending through the first gap and coupled to the chip contacts of the first microelectronic element, and second wire bonds extending through the second gap and coupled to the chip contacts of the second microelectronic element, the edge contacts being coupled to the first and second microelectronic elements through the first and second wire bonds; and
an encapsulant covering the first and second microelectronic elements and a portion of the lead assembly.
2. The module as claimed in claim 1, wherein chip contacts of the second microelectronic element are exposed within a central region of the front surface of the second microelectronic element.
3. The module as claimed in claim 2, wherein chip contacts of the first microelectronic element are exposed within a central region of the front surface of the first microelectronic element.
4. The module as claimed in claim 1, wherein the first microelectronic element has a second edge opposed to the lateral edge, the front surface of the first microelectronic element and the lateral and second edges of the first microelectronic element being such that:
the front surface of the first microelectronic element has a first outer region adjacent the lateral edge of the first microelectronic element, a second outer region adjacent the second edge of the first microelectronic element, and a central region disposed between the first and second outer regions of the front surface of the first microelectronic element, each of the first and second outer regions and the central region having equal width such that the central region of the first microelectronic element extends a middle third of a distance between the lateral and second edges, wherein the chip contacts of the first microelectronic element are disposed in such central region.
5. The module as claimed in claim 1, wherein at least one of the first and second microelectronic elements includes a memory storage element.
6. The module as claimed in claim 5, wherein the lead assembly includes portions of leads extending from address input chip contacts of the at least one of the first and second microelectronic elements to a subset of the edge contacts, wherein the subset of the edge contacts are configured to carry an address signal usable to address the memory storage element in at least one of the first and second microelectronic elements.
7. The module as claimed in claim 1, wherein at least some of the edge contacts are configured to carry at least one of a signal or a reference potential between the respective edge contact and signal or reference potential chip contacts of each of the first and second microelectronic elements.
8. The module as claimed in claim 1, wherein at least one of the first and second microelectronic elements is flip chip bonded to the lead assembly.
9. The module as claimed in claim 1, further comprising a plurality of third microelectronic elements, each third microelectronic element being electrically connected to the lead assembly.
10. The module as claimed in claim 9, wherein the plurality of third microelectronic elements are arranged in a stacked configuration, each of the third microelectronic elements having a front or rear surface confronting a front or rear surface of an adjacent one of the third microelectronic elements.
11. The module as claimed in claim 9, wherein the plurality of third microelectronic elements are arranged in a planar configuration, each of the third microelectronic elements having a peripheral surface confronting a peripheral surface of an adjacent one of the third microelectronic elements.
12. The module as claimed in claim 9, wherein the second microelectronic element includes volatile RAM, the third microelectronic elements each include nonvolatile flash memory, and the first microelectronic element includes a processor having structure therein that is configured to predominantly control transfers of data between an external component and the second and third microelectronic elements.
13. The module as claimed in claim 9, wherein the second microelectronic element includes a volatile frame buffer memory storage element, the third microelectronic elements each include nonvolatile flash memory, and the first microelectronic element includes a graphics processor.