1. A printing apparatus, comprising:
a reading unit adapted to read a document image;
an extraction unit adapted to extract application data from the document image read by said reading unit;
a first determination unit adapted to determine whether a license to direct-print the application data extracted by said extraction unit is permitted;
a second determination unit adapted to determine, if it is determined by said first determination unit that a license to direct-print the application data extracted by said extraction unit is not permitted, whether a temporary licensing key is recorded in the document image read by said reading unit; and
a processing unit is adapted to,
a) if it is determined by said first determination unit that a license to direct-print the application data extracted by said extraction unit is permitted, analyze the application data extracted by said extraction unit and generate bitmap data,
b) if it is determined by said second determination unit that the temporary licensing key is recorded in the document image read by said reading unit, temporarily permit a license to direct-print, analyze the application data extracted by said extraction unit, generate bitmap data, print the bitmap data and return the temporarily permitted license to direct-print to original state.
2. The apparatus according to claim 1, wherein the processing unit,
if it is determined by the first determination unit that a license to direct-print the application data extracted by said extraction unit is permitted, analyzes the application data extracted by said extraction unit, generates bitmap data, and counts up a charging counter;
if it is determined by the second determination unit that the temporary licensing key is recorded in the document image read by said reading unit, temporally permits a license to direct-print, analyzes the application data extracted by said extraction unit, generates bitmap data, prints the bitmap data, counts up a licensing charging counter, and returns the temporarily permitted license to direct-print to original state; and
if it is determined by the second determination unit that the temporary licensing key is not recorded in the document image read by said reading unit, displays an error notification window.
3. A control method for printing apparatus, comprising,
a reading step of reading a document image;
an extraction step of extracting application data from the document image read in said reading step;
a first determination step of determining whether a license to direct-print the application data extracted in said extraction step is permitted;
a second determination step of determining, if it is determined in said first determination step that a license to direct-print the application data extracted in said extraction step is not permitted, whether a temporary licensing key is recorded in the document image read in said reading step; and
a processing step of,
a) if it is determined in said first determination step that a license to direct-print the application data extracted in said extraction step is permitted, analyzing the application data extracted in said extraction step and generating bitmap data,
b) if it is determined in said second determination step that the temporary licensing key is recorded in the document image read in said reading step, temporarily permitting a license to direct-print, analyzing the application data extracted in said extraction step, generating bitmap data, print the bitmap data and returning the temporarily permitted license to direct-print to original state.
4. The method according to claim 3, wherein the processing step,
if it is determined in the first determination step that a license to direct-print the application data in said extraction step is permitted, analyzes the application data extracted in said extraction step, generates bitmap data, counts up a charging counter;
if it is determined in the second determination step that the temporary licensing key is recorded in the document image read in said reading step, temporally permits a license to direct-print, analyzes the application data extracted in said extraction step, generates bitmap data, prints the bitmap, counts up a licensing charging counter, and returns the temporarily permitted license to direct-print to original state; and
if it is determined in the second determination step that the temporary licensing key is not recorded in the document image read in said reading step, displays an error notification window.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A writing driver circuit of a phase-change memory array, comprising:
a pulse selection circuit that outputs a selected one of a reset pulse and a set pulse in response to a logic level of data and the data;
a current control circuit that receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs the control signal at a first level during an enable duration of the set pulse when the data is at a second level; and
a current drive circuit that outputs writing current to the phase-change memory array in response to the control signal during the enable duration of the reset pulse or of the set pulse.
2. The writing driver circuit of claim 1, wherein at least one of the first level and the second level of the control signal increases or decreases in response to a change of the bias voltage.
3. The writing driver circuit of claim 1, wherein the enable duration of the reset pulse is shorter than the enable duration of the set pulse.
4. The writing driver circuit of claim 1, wherein a level of the writing current when the reset pulse is selected in the pulse selection circuit is higher than a level of the writing current when the set pulse is selected in the pulse selection circuit.
5. The writing driver circuit of claim 1, wherein the pulse selection circuit includes:
a first transmitter, which passes the reset pulse in response to the first logic level of the data;
a second transmitter, which passes the set pulse in response to the second logic level of the data;
a buffer that buffers the data and outputs the buffered data to the current control circuit; and
a first inverter that inverts an output of the first transmitter or the second transmitter and applies the inverted output to the current drive circuit.
6. The writing driver circuit of claim 5, wherein the first transmitter and the second transmitter include transmission gates which are turned on or off in response to the data and the inverted data, and wherein when either of the first transmitter and the second transmitter is turned on, the other transmitter is turned off.
7. The writing driver circuit of claim 6, wherein the buffer includes:
a second inverter which inverts the data to generate the inverted data; and
a third inverter which inverts the inverted data and outputs the data to the current control circuit.
8. The writing driver circuit of claim 1, wherein the current control circuit includes:
a first level controller which is turned on in response to the bias voltage and controls the level of the control signal to be generated at the first level during an enable duration of the set pulse;
a second level controller, which controls the level of the control signal to be generated at the second level in during an enable duration of the reset pulse;
a first control transistor which activates the current control circuit in response to the reset pulse or the set pulse; and
a second control transistor which turns deactivates the current control circuit and outputs the control signal at a third level during the disable duration of the reset pulse or the set pulse.
9. The writing driver circuit of claim 8, wherein the first level controller includes a first level transistor and a second level transistor which are connected in series between a drain of a first transistor and the drain of the first control transistor, the bias voltage being applied to gates of the first level transistor and the second level transistor, and the second level controller includes a third level transistor and a fourth level transistor which are connected in series between the drain of the first transistor and the drain of the first control transistor, the data being applied to gates of the third level transistor and the fourth level transistor.
10. The writing driver circuit of claim 9, wherein the first control transistor has a drain commonly connected to sources of the second and fourth level transistors, a source connected to a second voltage, and a gate to which the reset pulse or the set pulse is applied, and the second control transistor has a source connected to a first voltage, a drain connected to the drain of the first transistor, and a gate to which the reset pulse or the set pulse is applied.
11. The writing driver circuit of claim 9, wherein the current drive circuit includes:
a pull up transistor having a source connected to the first voltage, a drain connected to the first node, and a gate to which the control signal is applied; and
a pull down transistor having a drain connected to the first node, a source connected to the second voltage, and a gate to which an inverted reset pulse or an inverted set pulse is applied.
12. The writing driver circuit of claim 11, wherein the second level of the control signal is a voltage level which turns on the pull up transistor more than the first level of the control signal, and the third level of the control signal is a voltage level which turns off the pull up transistor.
13. A writing driver circuit of a phase-change memory array, comprising:
a pulse selection circuit that outputs a selected one of a reset pulse and a set pulse in response to a logic level of data;
a current control circuit that receives a bias voltage, the data and the selected one of a reset pulse and a set pulse, and outputs a control signal at a second level when the data is at a first level during an enable duration of the reset pulse , and outputs a control signal at a first level when the data is at a second level during an enable duration of the set pulse, and outputs a control signal at a third level during a disable duration of the reset pulse or the set pulse; and
a current drive circuit that outputs writing current at a first level or a second level to the phase-change memory array during an enable duration of the reset pulse or the set pulse respectively.
14. The writing driver circuit of claim 12, wherein the level of the at least one of the first level and the second level of the control signal increases or decreases in response to a change of the bias voltage.
15. The writing driver circuit of claim 12, wherein the first level of the writing current is higher than the second level of the writing current.
16. The writing driver circuit of claim 12, wherein the pulse selection circuit includes:
a first transmitter which passes the reset pulse in response to a logic level of the data;
a second transmitter which passes the set pulse in response to a logic level of the data.
17. The writing driver circuit of claim 16, wherein the first transmitter and the second transmitter include transmission gates which are turned on or off in response to the data, and wherein when either of the first transmitter and the second transmitter is turned on, the other transmitter is turned off.
18. The writing driver circuit of claim 13, wherein the current drive circuit includes:
a second level controller which outputs the writing current at a first level through a first node in response to the control signal during the enable duration of the reset pulse when the inverted data is at a second level;
a pull up transistor which outputs the writing current at a second level through the first node in response to the control signal during the enable duration of the set pulse when the inverted data is at a first level; and
a pull down transistor which discharges the first node during the disable duration of the reset pulse or the set pulse irrespective of a logic level of the data.
19. A writing driver circuit of a phase-change memory array, comprising:
a pulse selection circuit that receives a reset pulse and a set pulse and outputs a selected one of the reset pulse and the set pulse in response to the logic level of data;
a current drive circuit that outputs writing current at a first level or a second level to the phase-change memory array during an enable duration of the reset pulse or the set pulse respectively.
20. The writing driver circuit of claim 19, wherein the current drive circuit includes a first pull-up transistor and a second pull-up transistor connected in parallel between a first voltage and a first node; and wherein
the current drive circuit outputs writing current at the first level when the first pull-up transistor is activated during an enable duration of the reset pulse; and wherein
the current drive circuit outputs writing current at the second level when the first pull-up transistor and the second pull-up transistor are activated during an enable duration of the set pulse.