1. A process comprising:
polymerizing
(a) propylene,
(b) at least one C4-C8 \u03b1-olefin, and
(c) optionally ethylene, wherein the polymerizing step is carried out in the gas-phase,
wherein the process is carried out in a reactor having two interconnected polymerization zones, a riser and a downcomer,
wherein polymer particles flow through the riser under fast fluidization conditions, leave said riser and enter the downcomer,
wherein the polymer particles in the downcomer flow downward in a densified form, leave said downcomer and are reintroduced into said riser, thus establishing a circulation of polymer between the riser and the downcomer,
wherein a gas mixture present in the riser is prevented from entering the downcomer by introducing a liquid barrier into an upper part of said downcomer, thereby creating a recycle gas mixture that flows upward to a separation zone wherein the liquid barrier comprises at least one C4-C8 \u03b1-olefin in a total amount of from 0.1% to 35% by mol, and has a composition different from the gas mixture present in the riser,
wherein the recycle gas is separated into:
(i) a first stream of recycled gas, wherein the first stream of recycled gas is fed into a bottom part of the downcomer,
(ii) a second stream of recycled gas, wherein the second stream of recycled gas is fed into a bottom part of the riser; and
(iii) a third stream of recycled gas, wherein the third stream of recycled gas is fed into at least one distillation column before being recycled into the downcomer.
2. The process according to claim 1, wherein the partial evaporation of said liquid barrier generates in the upper part of the downcomer a flow of gas moving counter-currently to the flow of descendent polymer.
3. The process according to claim 1, wherein the C4-C8 \u03b1-olefin is 1-hexene and its amount ranges from 0.1% to 10% by mol.
4. The process according to claim 3, wherein the liquid barrier further comprises:
from 70 to 90% by mol of propylene;
from 5 to 15% by mol of propane; and
from 0 to 5% by mol of ethylene.
5. The process according to claim 4, wherein the obtained polyolefin contains from 0.2 to 8.0% by weight of recurring units derived from 1-hexene.
6. The process according to claim 1, wherein the C4-C8 \u03b1-olefin is 1-butene and its amount ranges from 2% to 30% by mol.
7. The process according to claim 6, wherein the liquid barrier further comprises:
from 50 to 90% by mol of propylene;
from 5 to 15% by mol of propane; and
from 0 to 5% by mol of ethylene.
8. The process according to claim 7, wherein the obtained polyolefin contains from 1 to 25% by weight of recurring units derived from 1-butene.
9. The process according to claim 1, wherein the liquid barrier derives from condensation andor distillation of a part of the gaseous stream continuously recycled to said reactor having two interconnected polymerization zones.
10. The process according to claim 9, wherein the composition of the liquid barrier is adjusted by feeding liquid make-up monomers and propane before introducing said liquid barrier into the upper part of the downcomer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a memory cell which is formed over a semiconductor substrate and includes a laminated structure of a TMR film and an upper electrode formed in a portion over a lower electrode and the lower electrode;
an antioxidant film which is formed covering an upper surface of the lower electrode, and a side surface of the TMR film at least, about the memory cell; and
an oxide film formed over the antioxidant film.
2. A semiconductor device according to claim 1, wherein
the antioxidant film covers a side surface of the lower electrode further.
3. A semiconductor device according to claim 1, wherein
the antioxidant film includes a plurality of antioxidant films.
4. A semiconductor device according to claim 1, further comprising:
a read wire which separates a predetermined distance from the TMR film in plan view and is formed under the lower electrode; and
a metal plug which is formed over the read wire and electrically connects the read wire and the lower electrode.
5. A semiconductor device according to claim 1, wherein
the upper electrode includes a hard mask layer which was formed using the same material as the lower electrode, which has conductivity, and whose thickness is 30-100 nm.
6. A semiconductor device, comprising:
a memory cell which is formed over a semiconductor substrate and includes a laminated structure of a TMR film and an upper electrode which were formed in a portion over a lower electrode and the lower electrode;
a read wire which separates a predetermined distance from the TMR film in plan view and is formed under the lower electrode; and
a metal plug which is formed over the read wire and electrically connects the read wire and the lower electrode.
7. A semiconductor device according to claim 6, wherein
the upper electrode includes a hard mask layer which was formed using the same material as the lower electrode, which has conductivity, and whose thickness is 30-100 nm.
8. A semiconductor device, comprising:
a memory cell which is formed over a semiconductor substrate and includes a laminated structure of a TMR film and an upper electrode which were formed in a portion over a lower electrode and the lower electrode;
wherein the upper electrode is a hard mask layer which was formed using the same material as the lower electrode, which has conductivity, and whose thickness is 30-100 nm.
9. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a laminated structure of a TMR film layer and an upper electrode layer which were formed over a lower electrode layer and the lower electrode layer over a semiconductor substrate;
(b) patterning the upper electrode layer and the TMR film layer;
(c) forming a first antioxidant film covering the lower electrode layer, the upper electrode, and the TMR film;
(d) patterning the first antioxidant film and the lower electrode layer after the first antioxidant film has covered the upper electrode and the TMR film; and
(e) forming an oxide film in a whole surface.
10. A method of manufacturing a semiconductor device, further comprising a step of:
(f) performing after the step (d) and before the step (e), and forming a second antioxidant film covering the first antioxidant film and the lower electrode;
wherein the step (e) includes a step which forms an oxide film all over the second antioxidant film being included.
11. A method of manufacturing a semiconductor device according to claim 9, wherein
the step (a) comprises the steps of:
(a-1) forming a read wire over the semiconductor substrate;
(a-2) forming an interlayer insulation film over the read wire;
(a-3) forming a via hole, penetrating the interlayer insulation film over the read wire;
(a-4) forming a metal plug embedding the via hole; and
(a-5) forming the laminated structure over the interlayer insulation film including the via hole;
wherein
the lower electrode in the laminated structure is electrically connected with the read wire via the metal plug; and
at the step (b), the TMR film after patterning is formed separating a predetermined distance from the read wire in plan view.
12. A method of manufacturing a semiconductor device according to claim 9, wherein
the upper electrode includes an electrode which was formed using the same material as the lower electrode and whose thickness is 30-100 nm; and
the step (b) comprises the steps of:
(b-1) patterning the upper electrode layer; and
(b-2) patterning the TMR film layer using the upper electrode as a hard mask layer.
13. A method of manufacturing a semiconductor device according to claim 9, wherein
the antioxidant film includes a silicon nitride film formed below or equal to 300\xb0 C.
14. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a read wire over a semiconductor substrate;
(b) forming an interlayer insulation film over the read wire;
(c) forming a via hole, penetrating the interlayer insulation film over the read wire;
(d) forming a metal plug, embedding the via hole; and
(e) forming a laminated structure of a lower electrode, a TMR film, and an upper electrode over the interlayer insulation film comprising the via hole;
wherein
the lower electrode is electrically connected with the read wire via the metal plug, and further comprising a step of:
(f) patterning the upper electrode layer and the TMR film layer;
wherein
the TMR film after patterning is formed, separating a predetermined distance in plan view from the read wire.
15. A method of manufacturing a semiconductor device according to claim 14, wherein
the upper electrode includes an electrode whose thickness is 30-100 nm formed using the same material as the lower electrode; and
the step (f) comprises the steps of:
(f-1) patterning the upper electrode layer; and
(f-2) patterning the TMR film layer using the upper electrode as a hard mask layer.
16. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a laminated structure of a lower electrode layer, a TMR film layer, and an upper electrode layer over a semiconductor substrate;
(b) patterning the upper electrode layer; and
(c) patterning the TMR film layer using the upper electrode as a hard mask layer.
17. A semiconductor device, comprising:
a first interlayer insulation film formed above a semiconductor substrate;
a lower layer wiring which penetrates the first interlayer insulation film and is formed selectively; and
a second interlayer insulation film formed over the first interlayer insulation film including the lower layer wiring;
wherein the second interlayer insulation film has a via hole where at least a part of the lower layer wiring constitutes a bottom; and further comprising a lower electrode formed at a bottom and a side surface of the via hole, and over the second interlayer insulation film; wherein the lower electrode is electrically connected with the lower layer wiring via the via hole; and further comprising a TMR element which is formed selectively over a portion over the lower electrode, and includes a laminated structure of a TMR film and an upper electrode; and an insulating film formed over the lower electrode comprising an inside of the via hole; wherein both the insulating film and the lower electrode have a side surface over the second interlayer insulation film in a uniform direction; and a side surface of the lower electrode corresponds in an uniform direction to a side surface of the insulating film, or a side surface of the lower electrode is depressed from the insulating film.
18. A semiconductor device according to claim 17, wherein
the insulating film includes a low-temperature insulation film formed at a low temperature less than or equal to 300\xb0 C.
19. A semiconductor device according to claim 17, wherein
the insulating film is formed over a whole surface over the lower electrode over the second interlayer insulation film.
20. A semiconductor device according to claim 17, wherein
a side surface of the lower electrode is formed to correspond to a side surface of the insulating film in the uniform direction.
21. A semiconductor device according to claim 17, wherein
the semiconductor device has a first and a second TMR formation areas; and the TMR element, the lower electrode, and the insulating film are formed in each of the first and the second TMR formation areas; and further comprising a third interlayer insulation film formed over a whole surface over the second interlayer insulation film comprising the first and the second TMR formation areas; wherein insulated separation of a lower electrode of the first and the second TMR formation area is mutually done with the third interlayer insulation film directly formed over the second interlayer insulation film; and as for the second and third interlayer insulation film, in an interface and its neighboring region, chemical species are formed with the same material at least.
22. A semiconductor device according to claim 21, wherein
the second and third interlayer insulation film is formed by the manufacturing process of the same contents.
23. A semiconductor device according to claim 22, wherein
the second and third interlayer insulation film is formed in an interface and its neighborhood by a low-temperature insulation film formed at a low temperature less than 300\xb0 C. at least.
24. A semiconductor device according to claim 17, wherein
the semiconductor device has a first and a second TMR formation areas;
the TMR element includes a first and a second TMR elements formed in the first and second TMR formation area;
the insulating film includes a first and a second insulation films formed in the first and second TMR formation area, and the first and second insulation film has a side surface which separates a first gap and faces mutually;
the lower electrode includes a first and a second lower electrodes formed in the first and the second TMR formation areas, and the first and second lower electrode has a side surface which separates a second gap and faces mutually; and
the first insulation film and the first lower electrode make a direction which goes to the second TMR formation area from the first TMR formation area the uniform direction, and the second insulation film and the second lower electrode make a direction which goes to the first TMR formation area from the second TMR formation area the uniform direction; and further comprising a third interlayer insulation film formed over a whole surface over the second interlayer insulation film comprising the first and second TMR formation area; wherein by being formed between the first and second lower electrodes, the third interlayer insulation film does insulated separation of the first and second lower electrode; and
a side surface of the first and second lower electrode is formed to be depressed to a side surface of the first and second insulation film in the uniform direction; and further comprising an end portion oxidization region which adjoins a side surface of the first and the second lower electrode, and is formed in the first and second insulating film lower part.
25. A semiconductor device according to claim 24, wherein
the first and second lower electrode includes a metallic material with which it is a high melting point, and an oxide has insulation.
26. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a first interlayer insulation film above a semiconductor substrate;
(b) forming a lower layer wiring selectively, penetrating the first interlayer insulation film;
(c) forming a second interlayer insulation film over the first interlayer insulation film including the lower layer wiring; and
(d) forming a via hole, penetrating the second interlayer insulation film over the lower layer wiring;
wherein a bottom of the via hole becomes at least a part of the lower layer wiring; and further comprising the steps of:
(e) forming a lower electrode over a bottom and a side surface of the via hole, and the first interlayer insulation film;
wherein the lower electrode is electrically connected with the lower layer wiring via the via hole; and further comprising the steps of;
(f) forming selectively a TMR element used as a laminated structure of a TMR film and an upper electrode over the lower electrode over the second interlayer insulation film;
(g) forming an insulating film over the lower electrode comprising the via hole;
(h) forming a resist patterned over the insulating film;
(i) etching the lower electrode and the insulating film by using the resist as a mask, and patterns the lower electrode and the insulating film; and
(j) removing the resist.
27. A method of manufacturing a semiconductor device according to claim 26, wherein
the insulating film includes a low-temperature insulation film; and
the step (g) includes a step which forms the insulating film at a low temperature less than or equal to 300\xb0 C.
28. A method of manufacturing a semiconductor device according to claim 26, wherein
the step (j) includes at least one processing of ashing treatment and a wet cleaning treatment.
29. A method of manufacturing a semiconductor device according to claim 26, wherein
the semiconductor device has the first and second TMR formation area;
the TMR element includes a first and second TMR element formed in the first and second TMR formation area;
the insulating film includes a first and second insulation film formed in the first and second TMR formation area, and the first and second insulation film has a side surface which separates a prescribed interval and faces mutually after the step (i) execution;
the lower electrode includes a first and second lower electrode formed in the first and second TMR formation area, and the first and second lower electrode has a side surface which separates the prescribed interval and faces mutually after the step (i) execution; and
the step (j) includes ashing treatment, and by oxidizing in part from a side surface of the first and second lower electrode by the ashing treatment, a first and second end portion oxidization region is formed.
30. A method of manufacturing a semiconductor device according to claim 26, wherein
the semiconductor device includes an element formation region in which the TMR element is formed, and a peripheral region in which the TMR element is not formed;
the second interlayer insulation film includes a first partial interlayer insulation film, and a second partial interlayer insulation film formed over the first partial interlayer insulation film; and
the insulating film is formed with material with comparable thickness and the same chemical species as the second partial interlayer insulation film; and further comprising the steps of:
(k) forming a third interlayer insulation film all over performing after the step (j) and including the element formation region and the peripheral region;
(l) forming a partial via hole for periphery which penetrates the third interlayer insulation film and the second partial interlayer insulation film in the peripheral region at the same time of forming a partial via hole for TMR which penetrates the third interlayer insulation film in the element formation region; and
(m) forming a via hole for periphery which makes the first partial interlayer insulation film penetrate from the partial via hole for periphery in the peripheral region while making the insulating film penetrate furthermore from the partial via hole for TMR and forming the via hole for TMR in the element formation region; wherein
the third interlayer insulation film is formed with a material with which the insulating film, and the second partial interlayer insulation film differ from chemical species, and are formed with the same material as the second partial interlayer insulation film in chemical species.