1. A system for authenticating an encryption key before transmitting encrypted messages containing sensitive information, the system comprising:
a client device, the client device being a data processing system having at least one processor and at least one memory, the client device connected to a network and operative to transmit and receive data over the network;
a remote device, the remote device being a data processing system having at least one processor and at least one memory, the remote device connected to the network and operative to transmit data to and receive data from the client device;
a peripheral device operative to encrypt messages before passing the encrypted message to the client device for transmission to the remote device, the peripheral device having at least one processor and a memory containing a first key of a cryptographic key pair, the peripheral device operatively connected to only the client device,
wherein the remote device transmits a digital certificate to the client device, the digital certificate containing an encryption key and a first digital signature, the first digital signature issued by a certificate authority to verify the encryption key is associated with the remote device,
in response to receiving the digital certificate from the remote device, the client device passing the digital certificate, a root certificate associated with the digital certificate and a second digital signature to the peripheral device, the second digital signature associated with the root certificate and created using a second key of the cryptographic key pair,
in response to receiving the digital certificate, the root certificate and the second signature, the peripheral device uses the root certificate to certify the digital certificate and the first digital signature in the digital certificate to verify the encryption key in the digital certificate is associated with the remote device and the peripheral device retrieves the first key of the cryptographic key pair from the memory of the peripheral device and applies the first key of the encryption key pair to the second digital signature to verify the root certificate.
2. The system of claim 1 wherein the first key of the cryptographic key pair stored in the memory of the peripheral device is unalterable in the memory.
3. The system of claim 1 wherein the memory of the peripheral device is a read only memory.
4. The system of claim 1 wherein the memory of the peripheral device is a programmable read only memory.
5. The system of claim 1 wherein the memory of the peripheral device is an EPROM.
6. The system of claim 1 wherein the memory of the peripheral device is an EEPROM.
7. The system of claim 1 wherein the client device passes a certification path beginning with the digital certificate and ending with the root certificate to the peripheral device and the peripheral device uses the certification path with the root certificate to verify the digital certificate.
8. The system of claim 1 wherein the network is the Internet.
9. The system of claim 1 wherein the second signature is contained in a second digital certificate.
10. The system of claim 1 wherein if the peripheral device unsuccessfully verifies the public key in the first certificate and the root certificate, the peripheral device discontinues communication with the remote device through the client device.
11. The system of claim 1 wherein if the peripheral device successfully verifies the public key in the first certificate and the root certificate, the peripheral device negotiates a set of encryption keys and decryption keys with the remote device, the encryption keys and decryption keys never sent to the client device in an unencrypted form.
12. The system of claim 11 wherein the peripheral device generates a master secret which the peripheral device then encrypts with the encryption key before passing the encrypted master secret to the client device for transmission to the remote device.
13. A peripheral device comprising:
at least one processor; and
at least one memory containing a first key of a cryptographic key pair,
the peripheral device operatively connectable to a client device connected to a network, the client device operative to transmit messages to and receive messages from a remote device connected to the network,
the peripheral device operative to encrypt messages before passing the encrypted messages to the client device for transmission to the remote device,
wherein the peripheral device verifies an encryption key originated from the remote device by;
the client device receiving a digital certificate from the remote device, the digital certificate containing an encryption key and a first digital signature, the first digital signature issued by a certificate authority to verify that the encryption key is associated with the remote device,
in response to receiving the digital certificate from the remote device, the client device passing the digital certificate, a root certificate associated with the digital certificate and a second digital signature to the peripheral device, the second digital signature associated with the root certificate and created using a second key of the cryptographic key pair,
in response to receiving the digital certificate, the root certificate and the second signature, the peripheral device uses the root certificate to certify the digital certificate and the first digital signature in the digital certificate to verify the encryption key in the digital certificate is associated with the remote device and the peripheral device retrieves the first key of the cryptographic key pair from the memory of the peripheral device and applies the first key of the encryption key pair to the second digital signature to verify the root certificate.
14. The peripheral device of claim 13 wherein the first key of the cryptographic key pair stored in the at least one memory is unalterable.
15. The peripheral device of claim 13 wherein the at least one memory is a read only memory.
16. The peripheral device of claim 13 wherein the memory of the peripheral device is a programmable read only memory.
17. The peripheral device of claim 13 wherein the memory of the peripheral device is an EPROM.
18. The peripheral device of claim 13 wherein the memory of the peripheral device is an EEPROM.
19. The peripheral device of claim 13 wherein the client device passes a certification path beginning with the digital certificate and ending with the root certificate to the peripheral device and the peripheral device uses the certification path with the root certificate to verify the digital certificate.
20. The peripheral device of claim 13 wherein the network is the Internet.
21. The peripheral device of claim 13 wherein the second signature is contained in a second digital certificate.
22. The peripheral device of claim 13 wherein if the peripheral device unsuccessfully verifies the public key in the first certificate and the root certificate, the peripheral device discontinues communicating with the remote device through the client device.
23. The peripheral device of claim 13 wherein if the peripheral device successfully verifies the public key in the first certificate and the root certificate, the peripheral device negotiates a set of encryption keys and decryption keys with the remote device, the encryption keys and decryption keys never sent to the client device in an unencrypted form.
24. The peripheral device of claim 23 wherein the peripheral device generates a master secret which the peripheral device then encrypts with the encryption key before passing the encrypted master secret to the client device for transmission to the remote device.
25. A method of authenticating a remote server, the method comprising:
providing a client device operatively connected to a remote device over a network;
providing a peripheral device operatively connected to only the client device and having a memory containing a key;
the client device receiving a digital certificate containing an encryption key and a first signature from the remote device, the first signature issued by a certificate authority to verify the encryption key is associated with the remote device;
passing the digital certificate from the client device to the peripheral device;
passing a certification path beginning with the digital certificate and ending with a root certificate from the client device to the peripheral device;
the peripheral device verifying the encryption key in the digital certificate with the first signature in the digital certificate using the certification path including the root certificate;
passing a second signature certifying the root certificate to the peripheral device;
the peripheral device retrieving the key from the memory of the peripheral device; and
the peripheral device checking the second signature using the retrieved key to verify the root certificate.
26. The method of claim 25 wherein the key stored in the memory of the peripheral device is unalterable in the memory.
27. The method of claim 25 wherein the memory of the peripheral device is a read only memory.
28. The method of claim 25 wherein the memory of the peripheral device is a programmable read only memory.
29. The method of claim 25 wherein the memory of the peripheral device is an EPROM.
30. The method of claim 25 wherein the memory of the peripheral device is an EEPROM.
31. The method of claim 25 wherein the client device passes a certification path beginning with the digital certificate and ending with the root certificate to the peripheral device and the peripheral device uses the certification path with the root certificate to verify the digital certificate.
32. The method of claim 25 wherein the network is the Internet.
33. The method of claim 25 wherein the second signature is contained in a second digital certificate.
34. The method of claim 25 wherein if the peripheral device unsuccessfully verifies the key in the digital certificate and the root certificate, the peripheral device discontinues communication with the remote device through the client device.
35. The method of claim 25 wherein if the peripheral device successfully verifies the key in the digital certificate and the root certificate, the peripheral device negotiates a set of encryption keys and decryption keys with the remote device, the encryption keys and decryption keys never sent to the client device in an unencrypted form.
36. The method of claim 35 wherein the peripheral device generates a master secret which the peripheral device then encrypts with the encryption key before passing the encrypted master secret to the client device for transmission to the remote device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A complementary non-volatile memory cell comprising:
a p-channel transistor having a source region and a drain region separated by a first channel, the drain region being connected to a node; and
an n-channel transistor having a source region and a drain region separated by second channel, the drain region being connected to the node,
wherein the n-channel transistor and the p-channel transistor share a floating gate structure that extends over the first and second channel regions.
2. The complementary non-volatile memory cell according to claim 1, further comprising a select transistor having a first terminal connected to the node, and a second terminal connected to a read bit line.
3. The complementary non-volatile memory cell according to claim 2, wherein the p-channel transistor is formed in an n-type well region, and wherein the n-channel transistor and the select transistor are formed in a single p-type well region.
4. The complementary non-volatile memory cell according to claim 1, further comprising a control gate structure located adjacent to the floating gate structure.
5. The complementary non-volatile memory cell according to claim 4, further comprising means for applying a positive voltage on the control gate structure and a negative voltage on the source region of the p-channel transistor such that the floating gate structure is programmed by band-to-band tunneling of electrons.
6. The complementary non-volatile memory cell according to claim 4, further comprising means for applying a negative voltage on the control gate structure and a positive voltage on the source region of the n-channel transistor such that the floating gate structure is erased.
7. The complementary non-volatile memory cell according to claim 4, wherein the floating gate structure and the control gate structure comprise portions of two separate polycrystalline silicon layers such that the control gate structure is formed over the floating gate structure.
8. The complementary non-volatile memory cell according to claim 4, wherein the floating gate structure and the control gate structure comprise portions of a single polycrystalline silicon layer such that the control gate structure is formed next to the floating gate structure.
9. The complementary non-volatile memory cell according to claim 8, the control gate structure comprises a finger portion extending between elongated portions of the floating gate structure.
10. A complementary non-volatile memory cell comprising:
a p-channel transistor having a first source and a first drain separated by a first channel;
an n-channel transistor having a second source and a second drain separated by a second channel;
a floating gate structure extending over the first channel and the second channel, and a control gate structure formed adjacent to the floating gate structure,
wherein current flows through the first and second channels are controlled by a charge stored by the floating gate structure and a voltage applied to the control gate structure.
11. The complementary non-volatile memory cell according to claim 10, further comprising a conductor connected between the first drain of the p-channel transistor and the second drain of the n-channel transistor.
12. The complementary non-volatile memory cell according to claim 11, further comprising a select transistor having a first terminal connected to the second drain of the n-channel transistor, and a second terminal connected to a read bit line.
13. The complementary non-volatile memory cell according to claim 12, wherein the p-channel transistor is formed in an n-type well region, and wherein the n-channel transistor and the select transistor are formed in a single p-type well region.
14. The complementary non-volatile memory cell according to claim 10, further comprising means for applying a positive voltage on the control gate structure and a negative voltage on the source region of the p-channel transistor such that the floating gate structure is programmed by band-to-band tunneling of electrons.
15. The complementary non-volatile memory cell according to claim 10, further comprising means for applying a negative voltage on the control gate structure and a positive voltage on the source region of the n-channel transistor such that the floating gate structure is erased.
16. The complementary non-volatile memory cell according to claim 10, wherein the floating gate structure and the control gate structure comprise portions of two separate polycrystalline silicon layers such that the control gate structure is formed over the floating gate structure.
17. The complementary non-volatile memory cell according to claim 10, wherein the floating gate structure and the control gate structure comprise portions of a single polycrystalline silicon layer such that the control gate structure is formed next to the floating gate structure.
18. The complementary non-volatile memory cell according to claim 17, the control gate structure comprises a finger portion extending between elongated portions of the floating gate structure.
19. A method for controlling a non-volatile memory cell including a p-channel transistor, an n-channel transistor, a floating gate structure extending over channel regions of both the p-channel transistor and the n-channel transistor, and a control gate structure located adjacent to the floating gate structure, the method comprising:
applying a positive voltage on the control gate structure and a negative voltage on a source region of the p-channel transistor such that the floating gate structure is programmed by band-to-band tunneling of electrons, and
applying a negative voltage on the control gate structure and a positive voltage on the source region of the n-channel transistor such that the floating gate structure is erased by back tunneling of electrons from the floating gate structure to the source region of the n-channel transistor andor band-to-band hole injection into the floating gate structure.
20. The method according to claim 19, wherein a first drain region of the n-channel transistor is connected to a second drain region of the p-channel transistor, wherein the non-volatile memory cell further comprises a select transistor connected between a read bit line and the first and second drains, and wherein the method further comprises grounding the source region of the p-channel transistor, applying a positive voltage to the control gate and to the source region of the n-channel transistor, and turning on the select transistor,
wherein when the floating gate is programmed, the p-channel transistor is turned on and the read bit line is pulled to ground, and
wherein when the floating gate is erased, the n-channel transistor is turned on and the read bit line is pulled to a positive voltage.