1. A display device comprising:
a display area comprising a gate line and a data line; and
a gate driver connected to an end of the gate line, the gate driver comprising at least one stage integrated on a substrate and configured to output a gate voltage,
wherein the stage comprises a stage input terminal, a stage output terminal, an inverter signal output terminal, an inverter unit and an output unit,
wherein the inverter signal output terminal is coupled to an output of the inverter unit,
wherein the output unit comprises a first transistor and a first capacitor,
wherein the first transistor includes an input terminal applied with a clock signal, a control terminal coupled to the stage input terminal, and an output terminal coupled to the stage output terminal through which the gate voltage is output, and
wherein an inverter voltage output from the inverter unit is lower than the gate voltage output by the output unit,
wherein the stage further comprises a pull-down unit having a second transistor,
wherein the second transistor comprises a control terminal configured to receive an output of a next stage which is coupled to the inverter signal output terminal, an input terminal coupled to the stage output terminal, and an output terminal coupled to a first ground.
2. The display device of claim 1, wherein the inverter unit comprises at least two transistors configured to generate the inverter voltage.
3. The display device of claim 1, wherein the stage further comprises a noise removal unit having at least a first transistor pair, wherein the first transistor pair comprises a control terminal configured to receive the inverter voltage, an input terminal coupled to the control terminal of the first transistor of the output unit, and an output terminal connected to a second ground.
4. The display device of claim 3, wherein the pull-down unit further comprises a second transistor pair,
wherein the second transistor pair comprises a control terminal configured to receive the output of the next stage, an input terminal coupled to the control terminal of the first transistor of the output unit, and an output terminal coupled to the second ground.
5. The display device of claim 4, wherein the noise removal unit further comprises at least one transistor comprising a control terminal configured to receive an inverter voltage of an inverter unit of a previous stage, an input terminal coupled to the stage output terminal, and an output terminal connected to the first ground.
6. The display device of claim 4, wherein the pull-down unit further comprises a third transistor comprising a control terminal configured to receive the output of the next stage, an input terminal coupled to the transmitting signal output terminal, and an output terminal connected to the second ground.
7. The display device of claim 6, wherein at least one of the transistors comprises an oxide semiconductor.
8. The display device of claim 1, wherein the stage further comprises a transmitting signal generator having at least one transistor comprising an input terminal configured to receive the clock signal, a control terminal coupled to the control terminal of the first transistor, and an output terminal coupled to a transmitting signal output terminal configured to output a transmitting signal.
9. The display device of claim 8, wherein the stage further comprises a noise removal unit comprising at least one transistor comprising a control terminal configured to receive the inverter voltage of the inverter unit, an input terminal connected to the transmitting signal output terminal, and an output terminal coupled to the second ground.
10. The display device of claim 9, wherein the stage further comprises the pull-down unit further comprises at least a transistor pair including a control terminal configured to receive an output of a next stage, an input terminal connected to the control gate of the first transistor of the output unit, and an output terminal connected to the second around.
11. The display device of claim 10, further comprising a noise removal unit comprising at least one transistor comprising a control terminal configured to receive an inverter voltage of an inverter unit of a previous stage, an input terminal coupled to the stage output terminal, and an output terminal connected to the first ground.
12. The display device of claim 11, wherein the pull-down unit further comprises at least one transistor comprising a control terminal configured to receive the output of the next stage, and an input terminal coupled to the transmitting signal output terminal, and an output terminal connected to a second voltage.
13. The display device of claim 12, wherein the pull-down unit further comprises a second transistor pair configured to receive the output of the next stage, an input terminal connected to the control terminal of the first transistor and an output terminal connected to the second ground.
14. The display device of claim 13, wherein at least one of the transistors comprises an oxide semiconductor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A planar wave guide (PWG) having a first end for coupling to a light pump and a second end opposite to the first end comprising:
a first cladding layer;
a second cladding layer; and
a uniformly doped core layer between the first cladding layer and the second cladding layer, wherein the core layer is tapered having a smaller thickness at the first end and a larger thickness at the second end, and wherein a ratio of the core thickness to thickness of the cladding layers is smaller at the first end and larger at the second end.
2. The PWG of claim 1, wherein the first cladding layer and the second cladding layer have the same thickness along a length of the PWG.
3. The PWG of claim 2, wherein the first cladding layer and the second cladding layer are proportionally tapered along the length of the PWG and having a larger thickness at the first end and a smaller thickness at the second end to form the PWG with a uniform overall thickness along the length.
4. The PWG of claim 2, wherein the first cladding layer and the second cladding layer have a constant same thickness along the length of the PWG to form the PWG with a varying overall thickness along the length proportional to the varying thickness of the core layer.
5. The PWG of claim 2, wherein the core thickness has a taper ratio of 3:1 from one end to the other end of the PWG.
6. The PWG of claim 2, wherein the core thickness varies from about 25 microns at the first end to about 75 microns at the second end.
7. The PWG of claim 1, wherein the first cladding layer has a larger thickness than the second cladding layer, at any point along a length of the PWG.
8. The PWG of claim 7, wherein the first cladding layer is proportionally tapered along the length of the PWG having a larger thickness at the first end and a smaller thickness at the second end oppositely proportional to the thickness of the core layer and the second cladding layer has a constant thickness along the length of the PWG to form the PWG with a uniform overall thickness along its length.
9. The PWG of claim 8, wherein the second cladding layer is formed by coating a corresponding side of the core layer with a uniform layer of material that serves as an evanescent wave (e-wave) coating.
10. The PWG of claim 7, wherein the first cladding layer and the second cladding layer each have a constant thickness along the length of the PWG to form the PWG with a varying overall thickness along the length proportional to the varying length of the core layer.
11. An optical amplifier including the PWG of claim 1.
12. A Mach-Zehnder interferometer including the PWG of claim 1.
13. A wavelength division multiplexer including the PWG of claim 1.
14. A laser weapon including the PWG of claim 1.