It is claimed:
1. A method of simultaneously storing original and replacement data in a non-volatile memory system, comprising:
identifying the original and replacement data by the same logical address, and
distinguishing the replacement data from the original data by keeping track of the relative times that the original and replacement data have been programmed into the memory.
2. A method of storing and retrieving original and replacement data in a non-volatile memory system, comprising:
identifying units of the original and the replacement data by the same logical address,
reading units of data in an inverse order from an order in which they were programmed into the memory, and
distinguishing units of replacement data from units of original data having the same logical address by the order in which they are read.
3. In a non-volatile memory system having a plurality of blocks of memory storage elements that are individually organized into a plurality of pages of memory storage elements, a method of substituting new data for superceded data within at least one page of one of the plurality of blocks while data in at least another page of said one block is not replaced, comprising:
programming the new data into at least one page of said one or another of the plurality of blocks,
identifying the at least one page of superceded data and the at least one page of new data by a common logical address, and
recording a relative time of programming the new and the superceded data.
4. The method of claim 3, wherein the relative time of programming is recorded for the individual pages in which the new and superceded data are programmed, whereby the at least one page of new data is distinguishable from the at least one page of superceded data by their recorded relative times of programming.
5. The method of claim 3, wherein the relative time of programming is recorded for the individual blocks, thereby to identify an order of programming of individual blocks having data with a common logical address, and further wherein pages within the individual blocks are programmed in a designated order, whereby the new pages of data are distinguishable from superceded pages of data within an individual block by their relative positions within the block.
6. The method of claim 3, wherein the data in at least another page of said one block that is not replaced are not copied into said one or another block as part of substituting the new data for the superceded data.
7. The method of claim 3, wherein nothing is written into the at least one page of superceded data as part of substituting the new data for the superceded data.
8. The method of claim 4, wherein recording a relative time of programming the new and superceded data includes storing a value of a clock at each of the times that the new and superceded data are programmed.
9. The method of claim 4, wherein recording a relative time of programming the new and superceded data includes storing a different value of a sequence of numbers at each of the times that the new and superseded data are programmed.
10. The method of either of claims 8 or 9, wherein storing the value indicating a relative time of programming the new and superceded data includes storing the individual values within the same pages as the new and superceded data to which the values relate.
11. The method of claim 3, wherein programming the new data into at least one page of another said one or another of the plurality of blocks includes programming the new data into the first available unused pages within said one or another block in a predefined order.
12. The method of claim 3, wherein identifying the at least one page of superceded data and the at least one page of new data by a common logical address includes recording at least part of the common logical address in the individual pages as overhead data.
13. The method of claim 12, including building a table in volatile memory including multiple physical block addresses for the common logical address.
14. A method of reading data that has been updated according to claim 4, comprising:
reading pages of data from said one block and, if new data has been programmed thereinto, said another block,
identifying any multiple pages of data that have the same logical address,
utilizing the recorded relative time of programming the new and superceded data to identify the most current of any pages having the same logical address, and
assembling data in the most current of any pages having the same logical address along with pages in said at least another page of said one block that have not been updated.
15. A method of reading data that has been updated according to claim 5, comprising:
reading pages of data within said one and, if new data has been programmed thereinto, another block in a reverse order from which they were programmed, and
passing over any pages of data so read which have the same logical page address as a page whose data has already been read.
16. The method of either one of claims 14 or 15, additionally comprising operating the individual memory storage elements with more than two storage states, thereby storing more than one bit of data in each storage element, and reading pages of data includes reading the more than two storage states from the individual memory storage elements.
17. The method of any one of claims 3-9, additionally comprising operating storage elements of the individual memory cells with more than two storage states, thereby storing more than one bit of data in each storage element.
18. The method of claim 17, wherein the storage elements include individual floating gates.
19. The method of any one of claims 3-9, wherein the non-volatile memory system is formed within an enclosed card having an electrical connector along one edge thereof that operably connects with a host system.
20. A method of operating a non-volatile memory system having an array of memory storage elements organized into at least two sub-arrays, wherein the individual sub-arrays are divided into a plurality of non-overlapping blocks of storage elements wherein a block contains the smallest group of memory storage elements that are erasable together, and the individual blocks are divided into a plurality of pages of storage elements wherein a page is the smallest group of memory storage elements that are programmable together, comprising:
linking at least one block from individual ones of said at least two sub-arrays to form a metablock wherein its component blocks are erased together as a unit, and
updating pages of original data within any of the metablock component blocks less than all the pages within the block by programming replacement data into pages within another at least one block in only a designated one of the sub-arrays regardless of which sub-array the data being updated is stored.
21. The method of claim 20, wherein storing the original and replacement data includes:
identifying the original and replacement data by the same logical address to the memory system, and
distinguishing the replacement data from the original data by keeping track of the relative times that the original and replacement data have been programmed their respective pages of the memory.
22. A non-volatile memory system, comprising:
an array of non-volatile memory storage elements organized in blocks of storage elements, wherein an individual block contains the smallest group of storage elements that is erasable, and
a programming mechanism that writes into a first block an updated version of less than all of original data stored in a second block along with an indication of the later writing of the updated version,
an address mechanism that logically addresses both the original data and the updated version with the same address, and
a reading mechanism that distinguishes the updated version from the original data at least in part by the relative time by said indication of the later writing of the updated version.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit coupled to a first node of a first circuit, comprising:
a first transistor having a control terminal and a first current handling terminal coupled to the first node, and a second current handling terminal coupled to a second node;
a second transistor having a control terminal coupled to the first node, a first current handling terminal coupled to a first supply voltage, and a second current handling terminal coupled to the second node; and
a resistor coupled between the second node and a second supply voltage,
wherein the second transistor is N times larger than the first transistor, and when a voltage is applied to the first node, a resistance value being (N+1) times the resistance of the resistor is established at the first node.
2. The circuit of claim 1, wherein the first supply voltage is a positive supply voltage of the first circuit and the second supply voltage is a virtual ground node.
3. The circuit of claim 2, wherein the first and second transistors each comprises a NPN bipolar transistor, the second transistor having an emitter area N times larger than an emitter area of the first transistor.
4. The circuit of claim 2, wherein the first and second transistors each comprises a NMOS transistor, the width to length ratio of the second transistor being N times the width to length ratio of the first transistor.
5. The circuit of claim 1, wherein the first supply voltage is a virtual ground node and the second supply voltage is a positive supply voltage of the first circuit.
6. The circuit of claim 5, wherein the first and second transistors each comprises a PNP bipolar transistor, the second transistor having an emitter area N times larger than an emitter area of the first transistor.
7. The circuit of claim 5, wherein the first and second transistors each comprises a PMOS transistor, the width to length ratio of the second transistor being N times the width to length ratio of the first transistor.
8. The circuit of claim 1, wherein an output impedance of the second transistor is much larger than the resistance of the resistor.
9. The circuit of claim 1, wherein when a voltage is applied to the first node, a current flows in the resistor such that a voltage across the resistor is much greater than (1N)*VT, where VT is the thermal voltage kTq.
10. The circuit of claim 1, wherein the impedance at the second current handling terminal of the first and second transistors is much smaller than the resistance of the resistor.
11. A circuit, comprising:
a first resistance multiplier circuit providing a first resistance value at a first node, the first resistance multiplier circuit comprising:
a first transistor having a control terminal and a first current handling terminal coupled to the first node, and a second current handling terminal coupled to a third node;
a second transistor having a control terminal coupled to the first node, a first current handling terminal coupled to a first supply voltage, and a second current handling terminal coupled to the third node, wherein the second transistor is N times larger than the first transistor; and
a first resistor coupled between the third node and a fourth node;
a second resistance multiplier circuit providing a second resistance value at a second node, the second resistance multiplier circuit comprising:
a third transistor having a control terminal and a first current handling terminal coupled to the second node, and a second current handling terminal coupled to a fifth node;
a fourth transistor having a control terminal coupled to the second node, a first current handling terminal coupled to the first supply voltage, and a second current handling terminal coupled to the fifth node, wherein the fourth transistor is M times larger tan the third transistor, and
a second resistor coupled between the fourth node and the fifth node; and
a first bias current source coupled between the fourth node and a second supply voltage,
wherein when a first voltage is applied to the first node, the first resistance value being established at the first node is (N+1) times the resistance of the first resistor, and when a second voltage is applied to the second node, the second resistance value being established at the second node is (M+1) times the resistance of the second resistor.
12. The circuit of claim 11, wherein N is equal to M.
13. The circuit of claim 11, wherein the first supply voltage is a positive supply voltage and the second supply voltage is a virtual ground node.
14. The circuit of claim 13, wherein the first and second transistors each comprises a NPN bipolar transistor, the second transistor having an emitter area N times larger than an emitter area of the first transistor; and wherein the third and fourth transistors each comprises a NPN bipolar transistor, the fourth transistor having an emitter area M times larger than an emitter area of the third transistor.
15. A circuit coupled to an output terminal of an amplifier circuit for attenuating the gain of the amplifier circuit, the circuit comprising:
a first transistor having a control terminal and a first current handling terminal coupled to the output terminal of the amplifier circuit, and a second current handling terminal coupled to a second node;
a second transistor having a control terminal coupled to the output terminal of the amplifier circuit, a first current handling terminal coupled to a first supply voltage, and a second current handling terminal coupled to the second node, wherein the second transistor is N times larger than the first transistor, and
a resistor coupled between the second node and a second supply voltage,
wherein when a voltage is applied to the output terminal of the amplifier circuit, a resistance being (N+1) times the resistance of the resistor is established at the output terminal of the amplifier circuit, the resistance operating to attenuate the gain of the amplifier circuit.
16. A circuit coupled to differential output terminals of an amplifier circuit for attenuating the gain of the amplifier circuit, the amplifier circuit including a differential input stage and an active load stage, the circuit comprising:
a first resistance multiplier circuit providing a first resistance value at a first differential output terminal of the amplifier circuit, the first resistance multiplier circuit comprising:
a first transistor having a control terminal and a first current handling terminal coupled to the first differential output terminal, and a second current handling terminal coupled to a first node;
a second transistor having a control terminal coupled to the first differential output terminal, a first current handling terminal coupled to a first supply voltage, and a second current handling terminal coupled to the first node, wherein the second transistor is N times larger than the first transistor; and
a first resistor coupled between the first node and a second supply voltage; and
a second resistance multiplier circuit providing a second resistance value at a second differential output terminal of the amplifier circuit, the second resistance multiplier circuit comprising:
a third transistor having a control terminal and a first current handling terminal coupled to the second differential output terminal, and a second current handling terminal coupled to a second node;
a fourth transistor having a control terminal coupled to the second differential output terminal, a first current handling terminal coupled to the first supply voltage, and a second current handling terminal coupled to the second node, wherein the fourth transistor is M times larger than the third transistor; and
a second resistor coupled between the second node and the second supply voltage,
wherein when a first voltage is applied to the first differential output terminal of the amplifier circuit, the first resistance value being established at the first differential output terminal is (N+1) times the resistance of the first resistor, and when a second voltage is applied to the second differential output terminal of the amplifier circuit, the second resistance value being established at the second differential output terminal is (M+1) times the resistance of the second resistor, the first and second resistance values operating to attenuate the gain of the amplifier circuit.
17. The circuit of claim 16, wherein N is equal to M.
18. The circuit of claim 16, wherein the first supply voltage is a positive supply voltage and the second supply voltage is a virtual ground node.
19. The circuit of claim 18, wherein the first and second transistors each comprises a NPN bipolar transistor, the second transistor having an emitter area N times larger than an emitter area of the first transistor; and wherein the third and fourth transistors each comprises a NPN bipolar transistor, the fourth transistor having an emitter area M times larger than an emitter area of the third transistor.
20. A method for providing a first resistance value at a first node, comprising:
coupling a first transistor to the first node, the first transistor having a control terminal and a first current handling terminal both coupled to the first node and a second current handling coupled to a second node;
coupling a second transistor to the first node, the second transistor having a control terminal coupled to the first node, a first current handling terminal coupled to a first supply voltage, and a second current handling terminal coupled to the second node, the second transistor being N dines larger than the first transistor; and
coupling a resistor between the second node and a second supply voltage,
wherein when a voltage is applied to the first node, the first resistance value at the first node is (N+1) times the resistance of the resistor.