1. A semiconductor device comprising:
a semiconductor substrate having a memory cell region and a peripheral circuit region;
memory cells in the memory cell region;
buried word lines in a plurality of grooves of the semiconductor substrate in the memory cell region;
a first interlayer insulating film over the semiconductor substrate;
a first interconnect over the first interlayer insulating film in the peripheral circuit region; and
a via plug penetrating the semiconductor substrate and the first interlayer insulating film, the via plug being coupled to the first interconnect in the peripheral circuit region.
2. The semiconductor device according to claim 1, wherein the via plug is in contact with the first interconnect.
3. The semiconductor device according to claim 1, wherein the first interconnect comprises a local interconnect disposed on the first interlayer insulating film.
4. The semiconductor device according to claim 1, wherein the via plug includes a projecting portion that projects from the semiconductor substrate.
5. The semiconductor device according to claim 1, further comprising:
a first insulating film on a first surface of the semiconductor substrate,
wherein the first interlayer insulating film is disposed over a second surface of the semiconductor substrate, the second surface is opposite to the first surface,
wherein the via plug penetrates the first insulating film, the semiconductor substrate and the first interlayer insulating film, and
wherein the projecting portion projects from the first insulating film.
6. The semiconductor device according to claim 1, further comprising:
a first isolating film in the semiconductor substrate, the first isolating film surrounding the via plug in the semiconductor substrate, the first isolating film isolating the via plug from outside the first isolating film.
7. The semiconductor device according to claim 1, further comprising:
a capacitive contact pad disposed over the first interlayer insulating film, and the capacitive contact pad being in a memory cell region of the semiconductor substrate,
wherein the first interconnect comprises a local interconnect disposed over the first interlayer insulating film, the local interconnect being in a peripheral circuit region of the semiconductor substrate,
the capacitive contact pad comprises a first patterned portion of a conductive film, and
the first interconnect comprises a second patterned portion of the conductive film.
8. The semiconductor device according to claim 7, further comprising:
a capacitor being disposed in the memory cell region, the capacitor being coupled to the capacitive contact pad.
9. The semiconductor device according to claim 8, further comprising:
a second interlayer insulating film covering the capacitive contact pad and the first interconnect, the second interlayer insulating film burying the capacitor.
10. The semiconductor device according to claim 9, further comprising:
a third interlayer insulating film disposed over the second interlayer insulating film; and
multi-level interconnects buried in the third interlayer insulating film.
11. The semiconductor device according to claim 10, further comprising:
a first bump disposed over the third interlayer insulating film in the peripheral circuit region; and
a contact plug penetrating the second and third interlayer insulating films in the peripheral circuit region, the contact plug being coupled through the multi-level interconnects to the first bump, and the contact plug being coupled through the first interconnect to the via plug.
12. The semiconductor device according to claim 1, wherein the via plug comprises:
a copper bump;
a seed film covering side surfaces and a top surface of the copper bump, the top surface facing to the first interconnect; and
a metal film covering a bottom surface of the copper bump, the bottom surface being projected outside the semiconductor substrate.
13. A semiconductor device comprising:
a semiconductor substrate having a memory cell region and a peripheral circuit region;
a first interlayer insulating film over the semiconductor substrate;
a first local interconnect disposed over the first interlayer insulating film, the first local interconnect being in the peripheral circuit region, the first local interconnect comprising a first patterned portion of a conductive film;
a capacitive contact pad disposed over the first interlayer insulating film, the capacitive contact pad being in the memory cell region, the capacitive contact pad comprising a second patterned portion of the conductive film; and
a via plug penetrating the semiconductor substrate and the first interlayer insulating film, the via plug being coupled to the first local interconnect.
14. The semiconductor device according to claim 13, further comprising:
a capacitor being disposed in the memory cell region, the capacitor being coupled to the capacitive contact pad.
15. The semiconductor device according to claim 13, wherein the via plug includes a projecting portion that projects from the semiconductor substrate.
16. A semiconductor device comprising:
a semiconductor substrate having a memory cell region and a peripheral circuit region;
a first interlayer insulating film over the semiconductor substrate;
memory cells in the memory cell region;
buried word lines in a plurality of grooves of the semiconductor substrate in the memory cell region;
a first local interconnect disposed over the first interlayer insulating film, the first local interconnect being in the peripheral circuit region, the first local interconnect comprising a first patterned portion of a conductive film;
a capacitive contact pad disposed over the first interlayer insulating film, the capacitive contact pad being in the memory cell region, the capacitive contact pad comprising a second patterned portion of the conductive film;
a via plug penetrating the semiconductor substrate and the first interlayer insulating film, the via plug being coupled to the first interconnect, the via plug including a projecting portion that projects from the semiconductor substrate.
17. The semiconductor device according to claim 16, further comprising:
a capacitor being disposed in the memory cell region, the capacitor being coupled to the capacitive contact pad;
a second interlayer insulating film over the first interlayer insulating film, the second interlayer insulating film burying the first local interconnect and the capacitive contact pad;
a third interlayer insulating film over the second interlayer insulating film;
a fourth interlayer insulating film over the third interlayer insulating film;
a first bump over the fourth interlayer insulating film, the first bump being in the peripheral circuit region;
multi-level interconnects buried in the fourth interlayer insulating film, the multi-level interconnects being in the peripheral circuit region; and
a contact plug structure penetrating the second, third and fourth interlayer insulating films in the peripheral circuit region, the contact plug structure being coupled through the multi-level interconnects to the first bump, and the contact plug structure being coupled through the first local interconnect to the via plug.
18. The semiconductor device according to claim 17, further comprising:
a first isolating film in the semiconductor substrate, the first isolating film surrounding the via plug in the semiconductor substrate, the first isolating film isolating the via plug from outside the first isolating film.
19. The semiconductor device according to claim 17, further comprising:
a bottom insulating film on a first surface of the semiconductor substrate,
wherein the first interlayer insulating film is disposed over a second surface of the semiconductor substrate, the second surface is opposite to the first surface,
wherein the via plug penetrates the bottom insulating film, the semiconductor substrate and the first inter-layer insulating film, and
wherein the projecting portion projects from the first insulating film.
20. The semiconductor device according to claim 16, wherein the first local interconnect and the capacitive contact pad have substantially the same thickness and substantially the same material.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor package, comprising:
a lead frame having a plurality of leads, each of the leads being formed at an inner end thereof with a protruding portion that is dimensioned smaller in thickness than the rest part of the lead, wherein the protruding portion has at least a first surface and a second surface opposed to the first surface, and at least a first bonding region is defined on the first surface and staggered in position with a second bonding region formed on the second surface;
at least a first semiconductor chip having an active surface and a non-active surface opposed to the active surface, wherein the active surface faces downwardly and is connected to the first bonding regions by a plurality of bonding wires, so as to allow the first semiconductor chip to be electrically coupled to the leads;
at least a second semiconductor chip having an active surface and a non-active surface opposed to the active surface, and mounted on the first semiconductor chip, wherein the active surface is electrically connected to the second bonding regions by a plurality of conductive elements; and
an encapsulant for encapsulating the first and second semiconductor chips, the bonding wires and the conductive elements.
2. The semiconductor package of claim 1, wherein the semiconductor package is a QFN (quad flat non-lead) semiconductor package.
3. The semiconductor package of claim 1, wherein the protruding portions with smaller thickness form a cavity underneath the first surfaces of the protruding portions for receiving the bonding wires.
4. The semiconductor package of claim 1, wherein the first surface of the protruding portion is further defined with a bump corresponding region that is vertically aligned in position with the second bonding region.
5. The semiconductor package of claim 4, wherein the bump corresponding region is free of overlap with the first bonding region on the first surface of the protruding portion.
6. The semiconductor package of claim 1, wherein the bonding wires are bonded to the first bonding regions by using a wire bonder.
7. The semiconductor package of claim 6, wherein the wire bonder applies a force to the first bonding regions.
8. The semiconductor package of claim 1, wherein the conductive elements are solder bumps.
9. The semiconductor package of claim 1, wherein the non-active surface of the second semiconductor chip is exposed to outside of the encapsulant.
10. The semiconductor package of claim 1, wherein a heat sink is mounted on the nonactive surface of the second semiconductor chip.
11. A fabrication method of a semiconductor package, comprising the steps of:
preparing a lead frame having a plurality of leads, each of the leads being formed at an inner end thereof with a protruding portion that is dimensioned smaller in thickness than the rest part of the lead, wherein the protruding portion has at least a first surface and a second surface opposed to the first surface, and at least a first bonding region is defined on the first surface and staggered in position with a second bonding region formed on the second surface;
preparing at least a first semiconductor chip and a second semiconductor chip, and electrically connecting the second semiconductor chip to the second bonding regions by a plurality of conductive elements, wherein the second semiconductor chip is mounted on the first semiconductor chip;
placing the lead frame mounted with the first and second semiconductor chips into a jig, and forming a plurality of bonding wires for electrically connecting the first semiconductor chip to the first bonding regions; and
forming an encapsulant for encapsulating the first and second semiconductor chips, the bonding wires and the conductive elements.
12. The fabrication method of claim 11, wherein the semiconductor package is a QFN (quad flat non-lead) semiconductor package.
13. The fabrication method of claim 11, wherein the protruding portions with smaller thickness form a cavity underneath the first surfaces of the protruding portions for receiving the bonding wires.
14. The fabrication method of claim 11, wherein the first surface of the protruding portion is further defined with a bump corresponding region that is vertically aligned in position with the second bonding region.
15. The fabrication method of claim 14, wherein the bump corresponding region is free of overlap with the first bonding region on the first surface of the protruding portion.
16. The fabrication method of claim 11, wherein the conductive elements are solder bumps.
17. The fabrication method of claim 11, wherein the jig is composed of an upper part and a lower part opposed to the upper part, and the lower part is formed with a flat extending portion corresponding in position to the leads for supporting the protruding portions thereon.
18. The fabrication method of claim 11, wherein the bonding wires are bonded to the first bonding regions by using a wire bonder.
19. The fabrication method of claim 18, wherein the wire bonder applies a force to the first bonding regions.
20. The fabrication method of claim II, further comprising a step of: mounting a heat sink on the second semiconductor chip.