1-9. (canceled)
10. A separator or dust chamber (1) for separating solid particles from vapour-gas mixture, the separator comprising the main body (2) with internal refractory lining (7) placed on internal side-surface of said main body, first stage cyclone (3), second stage cyclone (4), lamella compensators (18, 19), dust removal conduits (5, 15), inlet conduit for vapour-gas mixture (13) to first stage cyclone (3), inlet vent (9) in the main body (2) of dust chamber (1) for vapour-gas mixture containing semi-coke particles wherein said diameter of the cylinder of the main body (2) of the dust chamber is uniform in its full height, with its lower end (11) having an outlet vent (8) for the removal of semi-coke particles, whereas said inlet vent (9) is located above the outlet vent (8) on the side of the main body (2) of dust chamber (1), and that the first and second stage cyclones (3, 4) are located outside the main body (2) of dust chamber (1).
11. The separator for separating solid particles from vapour-gas mixture according to claim 10 wherein said vapour-gas mixture inlet conduit (13) to first stage cyclone (3) is located vertically on the upper end (10) of said main body (2) of dust chamber (1), so that its axis is on the same direction and parallel to the vertical axis of the main body (2) of dust chamber.
12. The separator for separating solid particles from vapour-gas mixture according to claim 10 wherein said material of internal refractory lining (7) of main body (2) of dust chamber (1) is wear-proof and non-porous thermal insulation material.
13. The separator for separating solid particles from vapour-gas mixture according to claim 12 wherein said material of internal refractory lining (7) of main body (2) of dust chamber (1) is wear-proof and non-porous thermal insulation material is concrete.
14. The separator for separating solid particles from vapour-gas mixture according to claim 10 wherein said first and second stage cyclones (3, 4) are connected by dust channels (5) with the lower end (11) of said main body (2) of dust chamber (1) whereas dust channels (5) are directed above to the semi-coke outlet vent (8) located in said main body (2) of dust chamber (1).
15. The separator for separating solid particles from vapour-gas mixture according to claim 10 wherein said internal surface of first and second stage cyclones (3, 4) is lined with wear-proof material (16).
16. The separator for separating solid particles from vapour-gas mixture according to claim 15 wherein said wear-proof material (16) used for the internal surface of first and second stage cyclones (3, 4) is concrete.
17. The separator for separating solid particles from vapour-gas mixture according to claim 10 wherein said second stage cyclone (4) has a lower hydraulic resistance.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What I claim is:
1. A semiconductor device, comprising:
a semiconductor substrate having a grid-line area and a chip area, the chip area having a circuit area and a dummy area surrounding the circuit area;
circuit patterns formed on the substrate in the circuit area;
a first dummy pattern which is formed of the same material as the circuit pattern, formed in the dummy area, the dummy pattern encompassing the circuit area;
a first insulating layer formed on an entire surface of the semiconductor substrate;
a second insulating layer formed only on the first insulating layer which is formed on the semiconductor substrate and on the circuit patterns; and
a third insulating layer formed on the exposed first insulating layer and the second insulating layer.
2. A semiconductor device as claimed in claim 1, wherein the second insulating layer is a SOG layer.
3. A semiconductor device as claimed in claim 2, wherein the width of the first dummy pattern is fixed by a concentration of solid content of the SOG.
4. A semiconductor device as claimed in claim 1, wherein the width of the first dummy pattern is designed for less 1 m where a concentration of solid content of the SOG is around 5.2 wt %.
5. A semiconductor device as claimed in claim 1, further comprising, a second dummy patter formed under the first dummy pattern; and
a fourth insulating layer formed directly on the substrate and on the second dummy layer, the fourth insulating layer having characteristics that its surface is planarized by a thermal treatment,
whereby, the first dummy pattern is formed on the fourth insulating layer which is formed on the first dummy layer, and the circuit patterns are formed on the fourth insulating layer.
6. A semiconductor device as claimed in claim 5, wherein a shape and size of the second dummy pattern is almost the same as these of the first dummy pattern.
7. A semiconductor device as claimed in claim 5, wherein the fourth insulating layer is BPSG layer.
8. A semiconductor device as claimed in claim 5, wherein the second insulating layer is a SOG layer.
9. A semiconductor device as claimed in claim 6, wherein the widths of the first and second dummy patterns are fixed by a concentration of solid content of the SOG.
10. A semiconductor device as claimed in claim 6, wherein the widths of the first and second dummy patterns are designed for less 1 m where a concentration of solid content of the SOG is around 5.2 wt %.
11. A semiconductor device as claimed in claim 1, further comprising,
a third dummy pattern formed between the first dummy pattern and the circuit area, the first insulating layer being not formed on the third dummy pattern.
12. A semiconductor device as claimed in claim 11, wherein a width of the third dummy pattern is almost the same as that of the first dummy pattern.
13. A semiconductor device as claimed in claim 11, wherein the distance between the first dummy pattern and the second dummy pattern is designed for over 0.9 m.
14. A semiconductor device as claimed in claim 12, wherein the widths of the first and third dummy patterns are fixed by a concentration of solid content of the SOG.
15. A semiconductor device as claimed in claim 12, wherein widths of the first and third dummy patterns are designed for less 1 m where a concentration of solid content of the SOG is around 5.2 wt %.
16. A semiconductor device as claimed in claim 1, further comprising,
a bonding pad formed on the semiconductor substrate in the circuit area;
a fourth dummy pattern surrounding the bonding pad, the first insulating layer being not formed on the fourth dummy pattern.
17. A semiconductor device as claimed in claim 16, wherein a width of the fourth dummy pattern is almost the same as that of the first dummy pattern.
18. A semiconductor device as claimed in claim 16, wherein a distance between the fourth dummy pattern and the bonding pad is designed for over 0.9 m.
19. A semiconductor device as claimed in claim 17, wherein the widths of the first and fourth dummy patterns are fixed by a concentration of solid content of the SOG.
20. A semiconductor device as claimed in claim 117, wherein widths of the first and fourth dummy patterns are designed for less 1 m where a concentration of solid content of the SOG is around 5.2 wt %.
21. A method for manufacturing a semiconductor device, comprising,
preparing a semiconductor substrate having a grid-line area and a chip area, the chip area having a circuit area and a dummy area surrounding the circuit area;
forming a conductivity layer on the semiconductor substrate;
forming circuit patterns in the circuit area and a dummy pattern encompassing the circuit area in the dummy area by etching the conductivity layer;
forming a first insulating layer formed on an entire surface of the semiconductor substrate;
forming a second insulating layer formed only on the first insulating layer which is formed on the semiconductor substrate and on the circuit patterns;
forming a third insulating layer formed on the exposed first insulating layer and the second insulating layer; and
removing the first, second and third insulating layers in the grid-line area.
22. A method for manufacturing a semiconductor device as claimed in claim 21, wherein the second insulating layer is formed by a SOG method.
23. A method for manufacturing a semiconductor device, comprising,
preparing a semiconductor substrate having a grid-line area and a chip area, the chip area having a circuit area and a dummy area surrounding the circuit area;
forming a conductivity layer on the semiconductor substrate;
forming circuit patterns in the circuit area and a dummy pattern encompassing the circuit area in the dummy area by etching the conductivity layer;
forming a first insulating layer formed on an entire surface of the semiconductor substrate;
forming a second insulating layer on the first insulating layer;
removing the second insulating layer which is formed on the first insulating layer on the dummy pattern until the surface of the first insulating layer is exposed;
forming a third insulating layer formed on the exposed first insulating layer and on the second insulating layer; and
removing the first, second and third insulating layers in the grid-line area.
24. A method for manufacturing a semiconductor device as claimed in claim 23, wherein the second insulating layer is formed by a SOG method.
25. A method for manufacturing a semiconductor device as claimed in claim 23, wherein the second insulating layer is removed by a RIE method.
26. A method for manufacturing a semiconductor device as claimed in claim 23, wherein the second insulating layer is a multi-SOG layer.