1. An indicator light comprising: a body section defining a hole therethrough, clasps symmetrically protruding from opposite sides of the hole; a cover section detachably mounted to the body section, the cover section having a body portion, one side of the body portion including a protruding head portion, the head portion being received in the hole, opposite sides of the head portion defining symmetrical slits adjacent to the body portion and forming a stopping surface, the clasps for clasping the slits; a printed circuit body portion received in the body section; and a lamp electrically connected to the printed circuit body portion; wherein the lamp faces the cover section, so that the cover section guides lights from the lamp to the body section; wherein a body section defines a hole, the clasps symmetrically protrude from opposite sides of the hole, the cover section includes a head portion, symmetrical slits are defined at opposite sides of the head portion, the head portion is received in the hole, and the clasps clasp the slits; wherein the body section includes an interior surface defining two symmetrical slots on other opposite sides of the hole, the cover section includes a body portion being received in the slots.
2. The indicator light as claimed in claim 1, wherein the body section has an outer surface and an opposite interior surface, the printed circuit body portion adjacent to the interior surface.
3. The indicator light as claimed in claim 1, wherein the other side of the body portion includes a protruding tail portion, facing the lamp.
4. The indicator light as claimed in claim 1, wherein each clasp includes a clasping portion, the clasping portion has a guiding surface and a pressing surface opposite to the guiding surface, the pressing surface clasps the stopping surface.
5. The indicator light as claimed in claim 2, wherein the interior surface defines two symmetrical slots on other opposite sides of the hole, and the body portion is received in the slots.
6. The indicator light as claimed in claim 1, wherein the cover section is made of transparent and light-guiding material.
7. The indicator light as claimed in claim 1, wherein the lamp is an LED.
8. An indicator light, comprising: a body section being a part of a housing of an electronic device, the body section defining symmetrical clasps; a cover section detachably mounted to the body section, the cover section defining symmetrical slits, the clasps clasp the slits; a printed circuit body portion received in the body section; and a lamp electrically connected to the printed circuit body portion; wherein the lamp faces the cover section, so that the cover section guides lights from the lamp to the body section; wherein a body section defines a hole, the clasps symmetrically protrude from opposite sides of the hole, the cover section includes a head portion, symmetrical slits are defined at opposite sides of the head portion, the head portion is received in the hole, and the clasps clasp the slits; wherein the body section includes an interior surface defining two symmetrical slots on other opposite sides of the hole, the cover section includes a body portion being received in the slots.
9. The indicator light as claimed in claim 8, wherein each clasp includes a clasping portion, the clasping portion has a guiding surface and a pressing surface opposite to the guiding surface, each slit forms a stopping surface, and the pressing surface clasps the stopping surface.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for forming an intrinsic type microcrystalline silicon layer, comprising:
dynamically ramping up a silane gas supplied in a gas mixture to a surface of a substrate disposed in a processing chamber;
dynamically ramping down a RF power applied in the gas mixture supplied to the processing chamber, the gas mixture forming a plasma in the processing chamber; and
forming an intrinsic type microcrystalline silicon layer on the substrate in the presence of the plasma.
2. The method of claim 1, wherein the silane gas supplied in the gas mixture is ramped up linearly.
3. The method of claim 1, wherein the RF power applied in the gas mixture is ramped down linearly.
4. The method of claim 1, further comprising:
forming a seed layer prior to forming the intrinsic type microcrystalline silicon layer.
5. The method of claim 4, further comprising:
performing a hydrogen treatment process prior to forming the seed layer on the substrate surface.
6. The method of claim 4, wherein performing the hydrogen treatment process further comprises:
applying a RF power less than 150 milliWattscm2 in the hydrogen treatment process.
7. The method of claim 1, further comprising:
dynamically ramping up a process pressure of the gas mixture disposed in the processing chamber.
8. The method of claim 7, wherein dynamically ramping up the process pressure further comprises:
ramping up the process pressure from about 12 Torr to about 15 Torr.
9. The method of claim 1, wherein dynamically ramping up the silane gas supplied in the gas mixture further comprises:
ramping up a ratio of a flow rate of the silane gas to a hydrogen gas supplied in the gas mixture from about 1:70 to about 1:80.
10. The method of claim 1, wherein dynamically ramping down the RF power applied in the gas mixture further comprises:
ramping down the RF power from 800 milliWattscm2 to about 700 milliWattscm2.
11. The method of claim 1, further comprising:
dynamically increasing a spacing of the substrate from about 600 mils to about 700 mils.
12. The method of claim 4, wherein forming the seed layer further comprises:
ramping up a silane gas flow rate supplied in the gas mixture; and
maintaining a steady hydrogen gas flow rate supplied in the gas mixture while ramping up the silane gas flow rate.
13. The method of claim 5, wherein forming the seed layer further comprises:
applying a RF power less than 400 milliWattscm2 while forming the seed layer.
14. The method of claim 1, further comprising:
supplying the gas mixture to the processing chamber for a period between about 1000 seconds and about 1800 seconds.
15. A method for forming an intrinsic type microcrystalline silicon layer, comprising:
forming an intrinsic type seed layer on a substrate disposed in a processing chamber;
applying a RF power less than 400 milliWattscm2 to maintain a plasma formed from a gas mixture while forming the seed layer;
subsequently forming an intrinsic type microcrystalline silicon layer on the substrate in the presence of the plasma, wherein the intrinsic type microcrystalline silicon layer is formed by dynamically ramping up a silane gas supplied in the gas mixture; and
dynamically ramping down a RF power applied in the gas mixture supplied to the processing chamber to form a plasma in the gas mixture.
16. The method of claim 15, wherein the step of dynamically ramping up the silane gas supplied in the gas mixture further comprises:
ramping up a flow ratio of the silane gas to a hydrogen gas supplied in the gas mixture from about 1:70 to about 1:80.
17. The method of claim 15, wherein the step of dynamically ramping down the RF power further comprises:
ramping down the RF power from 800 milliWattscm2 to about 700 milliWattscm2.
18. The method of claim 15, the step of dynamically ramping up the silane gas supplied in the gas mixture further comprises:
ramping up the process pressure from about 12 Torr to about 15 Torr.
19. The method of claim 15, further comprising:
performing a hydrogen treatment process prior to forming the intrinsic type seed layer on the substrate surface.
20. A method for forming an intrinsic type microcrystalline silicon layer, comprising:
supplying a first gas mixture onto a surface of a substrate disposed in a processing chamber to form an intrinsic type seed layer on the substrate, wherein a first gas mixture includes a silane gas and a hydrogen gas, the silane gas flow rate is ramped up and the hydrogen gas flow rate is maintained steady while supplying the first gas mixture; and
supplying a second gas mixture onto the surface of the substrate to form an intrinsic type microcrystalline silicon layer on the intrinsic type seed layer, wherein the silane gas flow rate is ramped up while supplying the second gas mixture and a RF power applied to the second gas mixture is ramped down while forming the intrinsic type microcrystalline silicon layer.