1. (Cancelled)
2. The motion control system of claim 1, said actuators are selected from the group consisting of a voice coil motor and electroactive stack actuator.
3. The motion control system of claim 1, said sensors selected from the group consisting of LVDT, accelerometer, laser interferometer, capacitive displacement sensor.
4. The motion control system of claim 1, said circuit comprising a digital signal processor.
5. The motion control system of claim 1, said circuit comprising:
at least one digital signal processor,
at least one analog to digital converter, and
at least one digital to analog converter.
6. The motion control system of claim 1, said circuit comprising a control technique.
7. The control technique of claim 6, said control technique selected from the group of linear quadratic gaussian, H-infinity, and mu-synthesis.
8. The motion control system of claim 1, wherein said actuators stabilize said wafer stage base to closely follow a commanded input.
9. An motion control system for use with a lithography system, said motion control system comprising:
a wafer stage;
at least two actuators for controlling motion;
at least two sensors for detecting at least one parameter of displacement of said wafer base and producing at least two signals in response thereto;
a signal conditioner; and
a single board computer
wherein, upon the detection of said at least one parameter of displacement by said sensors, said sensors feed a signal to said signal conditioner, said signal conditioner feeds a signal to said single board computer, and said single board computer commands said actuators to command said wafer stage to track a commanded position.
10. The motion control system of claim 9, wherein said actuators are selected from the group consisting of voice coil motor and electroactive stack actuator.
11. The motion control system of claim 9, wherein said sensors are selected from the group consisting of LVDT, accelerometer, laser interferometer, capacitive displacement sensor.
12. The motion control system of claim 9, wherein said wafer stage is commanded to track a commanded position within 0.19 seconds.
13. A motion control system of claim 1, wherein said circuit comprises a processor programmed with a control algorithm derived from a mode based state-space model.
14. A system as in claim 13, wherein said state-space model is derived using a finite element model with fictitious masses.
15. A system as in claim 13, wherein said processor is an element of a linear quadratic Gausian controller.
16. The method of motion control comprising:
applying induced strain to an elastic portion of an operating machine utilizing at least one induced strain actuator, controlled by a computer processor programmed based upon a state space model;
wherein the state-space model is generated from a dynamic analysis of a simulation of the motion of the elastic portion of the operating machine occurring during the operation of the operating machine.
17. The method of claim 16 further comprising:
the dynamic analysis includes utilization of state-space equations of motion to facilitate the integration of control systems and response simulation employing a synthesis tool.
18. The method of claim 16 further comprising:
wherein the state-pace model is a reduced-order state-space model based upon a selected subset of elements from a Finite Element Model (FEM) including natural vibration modes within a selected excitation frequency range and selected modes for modal analysis.
19. The method of claim 17 further comprising:
wherein the state-pace model is a reduced-order state-space model based upon a selected subset of elements from a Finite Element Model (FEM) including natural vibration modes within a selected excitation frequency range and selected modes for modal analysis.
20. The method of claim 16 further comprising:
the dynamic analysis includes utilization f state-space equations of motion to facilitate the integration of control systems and response simulation employing a synthesis tool.
21. The method of claim 17 further comprising:
the dynamic analysis includes utilization f state-space equations of motion to facilitate the integration of control systems and response simulation employing a synthesis tool.
22. The method of claim 18 further comprising:
the dynamic analysis includes utilization f state-space equations of motion to facilitate the integration of control systems and response simulation employing a synthesis tool.
23. The method of claim 19 further comprising:
the dynamic analysis includes utilization f state-space equations of motion to facilitate the integration of control systems and response simulation employing a synthesis tool.
24. The method of claim 20, further comprising:
employing fictitious masses and complementary static load analysis to improve the model’s accuracy andor efficiency.
25. The method of claim 21, further comprising:
employing fictitious masses and complementary static load analysis to improve the model’s accuracy andor efficiency.
26. The method of claim 22, further comprising:
employing fictitious masses and complementary static load analysis to improve the model’s accuracy andor efficiency.
27. The method of claim 23, further comprising:
employing fictitious masses and complementary static load analysis to improve the model’s accuracy andor efficiency.
28. The method of claim 16, further comprising:
utilizing at least one electroactive actuator and high accuracy representation of the structure surrounding the actuator derived utilizing fictitious masses.
29. The method of claim 28 further comprising:
utilizing fictitious mass modal coupling to include the effects of local deformation around selected grid points on the elastic portion.
30. The method of claim 29, further comprising:
utilizing sets of low-frequency modes generated by a standard mode analysis procedure.
31. The method of claim 30, further comprising utilizing a fictitious mass matrix in a finite element model.
32. The method of claim 31, further comprising:
generating cleaned eigenvalues from FEM modes by removing the effects of the fictitious masses, and utilizing the eigenvalues when local response near the fictitious mass point if of interest.
33. The method of claim 16, further comprising:
utilizing electroactive elastic strain actuators to provide elastic vibration damping.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An integrated circuit device, comprising:
a DRAM interface circuit having clock, address, command and data driver circuits therein that support independent skew control in response to respective clock, address, command and data skew control signals.
2. The device of claim 1, wherein each of the clock, address, command and data driver circuits is responsive to a plurality of timing signals that represent multiple phases of an interface clock signal.
3. The device of claim 2, wherein each of the clock, address, command and data driver circuits is responsive to three (or six) timing signals that are phase-offset by 120\xb0 (or 60\xb0) relative to each other.
4. The device of claim 2, wherein the data driver circuit is a dual data rate (DDR) driver circuit that supports 2N bitssecond data rates, where N is a frequency of the interface clock signal.
5. The device of claim 2, wherein each of the clock, address, command and data driver circuits comprises a respective phase interpolator responsive to the plurality of timing signals.
6. The device of claim 2, wherein at least one of the clock, address, command and data driver circuits comprises an output buffer responsive to slew rate and impedance control signals.
7. The device of claim 1, wherein at least one of the clock, address, command and data driver circuits comprises an output buffer responsive to slew rate and impedance control signals.
8. The device of claim 1, wherein each of the clock, address, command and data driver circuits comprises an output buffer responsive to respective slew rate and impedance control signals.
9. An integrated circuit device, comprising:
a DRAM interface circuit having clock, address, command and data driver circuits therein that support independent skew, slew rate and impedance control in response to respective clock, address, command and data skew, slew rate and impedance control signals.
10. The device of claim 9, wherein each of the clock, address, command and data driver circuits is responsive to a plurality of timing signals that represent multiple phases of an interface clock signal.
11. The device of claim 10, wherein each of the clock, address, command and data driver circuits is responsive to three (or six) timing signals that are phase-offset by 120\xb0 (or 60\xb0) relative to each other.
12. The device of claim 10, wherein the data driver circuit is a dual data rate (DDR) driver circuit that supports 2N bitssecond data rates, where N is a frequency of the interface clock signal.
13. A DIMM-compatible memory buffer, comprising:
a dual data rate DRAM interface circuit having clock, address, command, data and strobe driver circuits therein that support independent skew control in response to respective clock, address, command, data and strobe skew control signals.
14. The device of claim 13, wherein each of the clock, address, command and data driver circuits is responsive to a plurality of timing signals that represent multiple phases of an interface clock signal.
15. The device of claim 14, wherein each of the clock, address, command and data driver circuits is responsive to three (or six) timing signals that are phase-offset by 120\xb0 (or 60\xb0) relative to each other.
16. A dual data rate DRAM interface circuit, comprising:
a clock driver circuit configured to generate an off-chip clock signal in response to an internal clock signal, a multi-bit clock skew control signal and a plurality of timing signals that represent multiple phases of an interface clock signal;
an address driver circuit configured to generate an off-chip address signal in response to an internal address signal, a multi-bit address skew control signal and the plurality of timing signals;
a command driver circuit configured to generate an off-chip command signal in response to an internal command signal, a multi-bit command skew control signal and the plurality of timing signals; and
a data driver circuit configured to generate a plurality of off-chip data signals in response to a plurality of internal data signals, a multi-bit data skew control signal and the plurality of timing signals.
17. The interface circuit of claim 16, further comprising a strobe driver circuit configured to generate an off-chip strobe signal in response to an internal strobe signal, a multi-bit strobe skew control signal and the plurality of timing signals.
18. The interface circuit of claim 17, wherein the plurality of timing signals represent multiple phases of an interface clock signal.
19. The interface circuit of claim 17, wherein the plurality of timing signals is three (or six) timing signals that are phase-offset by 120\xb0 (or 60\xb0) relative to each other.
20. The interface circuit of claim 16, wherein at least one of said address driver circuit, command driver circuit and said data driver circuit comprises an output buffer responsive to slew rate and impedance control signals.
21. An integrated circuit device, comprising:
a DRAM interface circuit having clock and data driver circuits therein that are responsive to a plurality of phases of an interface clock signal, said clock and data driver circuits configured to support independent skew control over a full period of the interface clock signal, in response to respective clock and data skew control signals.